
IBM32NPCXX1EPABBE66
Preliminary
IBM Processor for Network Resources
pnr261TOC.fm.06
August 14, 2000
Page i
Contents
List of Figures .............................................................................................................xvii
List of Tables ................................................................................................................xix
1. General Information .....................................................................................................1
1.1 Features ............................................................................................................................................1
1.2 Description .......................................................................................................................................1
1.3 Ordering Information .......................................................................................................................2
1.4 Conventions and Notation ..............................................................................................................2
1.5 Standards Compliance ....................................................................................................................3
1.6 References ........................................................................................................................................3
1.7 System Environment .......................................................................................................................4
1.7.1 Logical Channel Support ..........................................................................................................5
1.7.2 Virtual Memory Support ............................................................................................................5
1.7.3 Queues .....................................................................................................................................6
1.7.4 Scheduling ................................................................................................................................6
1.8 Key Interfaces ...................................................................................................................................7
1.9 Functional Description ....................................................................................................................9
1.9.1 Transmit Path .........................................................................................................................10
1.9.2 Receive Path ..........................................................................................................................11
1.9.3 Register Addressing Overview ...............................................................................................12
2. Input/Output Definitions ............................................................................................15
2.1 PCI Bus Interface ...........................................................................................................................15
2.2 DRAM Memory Bus Interface ........................................................................................................17
2.3 NPBUS Interface .............................................................................................................................21
2.4 PHY Bus Interface ..........................................................................................................................24
2.5 Clock, Configuration, and LSSD Interface ...................................................................................30
3. Register Descriptions by Entity ................................................................................33
3.1 The IOP Bus Specific Interface Controller (PCINT) .....................................................................33
3.1.1 PCI Options Taken .................................................................................................................33
3.1.2 PCI Target Response .............................................................................................................33
3.1.3 PCI Master Response ............................................................................................................33
3.1.4 PCI Master Retry ....................................................................................................................33
3.1.5 PCINT Config Word 0 .............................................................................................................34
3.1.6 PCINT Config Word 1 .............................................................................................................35
3.1.7 PCINT Config Word 2 .............................................................................................................37
3.1.8 PCINT Config Word 3 .............................................................................................................38
3.1.9 PCINT Base Address 1 (I/O for Register) ...............................................................................39
3.1.10 PCINT Base Address 2 (Mem for Register) .........................................................................41
3.1.11 PCINT Base Addresses 3-6 (Memory) .................................................................................43
3.1.12 PCINT CardBus CIS Pointer ................................................................................................45
3.1.13 PCINT Subsystem ID/Vendor ID ..........................................................................................46
3.1.14 PCINT ROM Base Address ..................................................................................................47
3.1.15 Capabilities Pointer ...............................................................................................................48