
IBM32NPCXX1EPABBE66
IBM Processor for Network Resources
Preliminary
Page xviii
pnr261LOF.fm.06
August 14, 2000
Figure 44: SRAM Read Cycle ...................................................................................................................674
Figure 45: SRAM Write Cycle ...................................................................................................................675
Figure 46: SRAM Read Cycle with Byte Enables .....................................................................................676
Figure 47: SRAM Write Cycle with Byte Enables .....................................................................................677
Figure 48: Parallel EPROM Read .............................................................................................................678
Figure 49: Parallel EPROM Write .............................................................................................................679
Figure 50: Serial EPROM Read ................................................................................................................680
Figure 51: Serial EPROM Write ................................................................................................................681
Figure 52: PHY Read ................................................................................................................................682
Figure 53: PHY Write ................................................................................................................................683
Figure 54: Transmit Packet Header Structure ..........................................................................................693
Figure 55: Receive Packet Header Structure ...........................................................................................693
Figure 56: Receive Packet Definitions ......................................................................................................694
Figure 57: Logical Channel Data Structure ...............................................................................................697
Figure 58: General LCD Layout ................................................................................................................697
Figure 59: Overall Transmit LCD Layout ..................................................................................................698
Figure 60: Scheduling Portion of a Transmit Descriptor ...........................................................................699
Figure 61: Transmit Logical Channel Descriptor Structure .......................................................................700
Figure 62: Transmit Logical Path Descriptor Structure .............................................................................701
Figure 63: Redefinition of Transmit Logical Channel Descriptor for Connections Sharing .......................702
Figure 64: Redefinition of Shared and Segmentation Portion of Transmit LCD for ABR ..........................703
Figure 65: Redefinition of Segmentation Portion of Transmit LCD for Fixed Size AAL5 Blocking ...........704
Figure 66: Redefinition of Segmentation Portion of Transmit LCD for MPEG2 ........................................704
Figure 67: Redefinition of Scheduling Portion of Transmit LCD for ABR ..................................................705
Figure 68: Redefinition of Scheduling Portion of Transmit LCD for Timers ..............................................705
Figure 69: Definition of LCD-Based Memory Management of Transmit LCD ...........................................706
Figure 70: Definition of ABR Code Variables ............................................................................................706
Figure 71: Transmit Data Structure Linkage .............................................................................................711
Figure 72: Basic Receive LCD Layout ......................................................................................................712
Figure 73: Raw LCD Packed and Miscellaneous Field Layouts ...............................................................713
Figure 74: Raw Routed LCD Packed and Miscellaneous Field Layouts ..................................................714
Figure 75: Raw Routed Early Drop LCD Packed and Miscellaneous Field Layouts ................................715
Figure 76: Raw Scatter/Cut-Through LCD Packed and Miscellaneous Field Layouts .............................716
Figure 77: AAL5 LCD Packed and Miscellaneous Field Layouts .............................................................717
Figure 78: AAL5 Routed LCD Layout .......................................................................................................718
Figure 79: AAL5 Cut-Through/Scatter Mode LCD Packed and Miscellaneous Field Layouts ..................719
Figure 80: Packet LCD Packed and Miscellaneous Field Layouts ...........................................................720
Figure 81: Packet Routed LCD Packed and Miscellaneous Field Layouts ...............................................721
Figure 82: Packet Cut-Through Scatter Mode LCD Packed and Miscellaneous Field Layouts ................722