- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67684 > IBM25PPC970MP7TR21AFT 64-BIT, 1600 MHz, RISC PROCESSOR, CBGA575 PDF資料下載
參數(shù)資料
| 型號(hào)： | IBM25PPC970MP7TR21AFT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1600 MHz, RISC PROCESSOR, CBGA575 |
| 封裝： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-575 |
| 文件頁(yè)數(shù)： | 54/74頁(yè) |
| 文件大?。?/td> | 845K |
| 代理商： | IBM25PPC970MP7TR21AFT |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)當(dāng)前第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)
Datasheet
PowerPC 970MP RISC Microprocessor
System Design Information
Page 58 of 74
Version 1.3
January 17, 2008
The bus frequency multiplier ratio typically indicates the desired PLL multiplier setting. Ratios based on multi-
ples of 3 (3:1, 6:1, 12:1) should always use PLLMULT = ‘0’ (low) for a PLL multiplier of 12. The required core
frequency should be divided by 12 to determine the required input SYSCLK frequency. Ratios based on multi-
ples of 2 (2:1, 4:1, 8:1, 24:1) should always use PLLMULT = ‘1’ (high) to multiply SYSCLK by 8.
Note: Using bus frequency ratios of 3:1, 6:1 or 12:1 with PLLMULT = ‘1’ or ratios of 8:1 or 24:1 with
PLLMULT = ‘0’ is not recommended. Internal clock synchronization delays might reduce performance.
After the correct BUS_CFG(0:2) and PLL_MULT pin settings are determined, the required SYSCLK input
frequency can be determined. The selected SYSCLK input frequency should be within the minimum and
maximum frequencies specified in Table 3-8 Clock ac Timing Specifications on page 27.
Table 5-1. PowerPC 970MP Bus Configuration
BUS_CFG(0:2)
Ratio
Notes
000
2:1
001
3:1
010
4:1
011
6:1
100
8:1
101
12:1
110
24:1
111
Not valid
Note: BUS_CFG bits can be changed by SCOM commands during the POR sequence. See the PowerPC 970MP RISC Microproces-
sor Design Guide and the PowerPC 970MP Power-On Reset Application Note.
1. Limited power-tuning frequency scaling.
2. Bus ratios of 8:1 and 24:1 are not supported for processor input (PI) functionality and power tuning.
3. No power-tuning frequency scaling.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM26BL486DX2-V66QP | 32-BIT, 66 MHz, MICROPROCESSOR, PQFP208 |
| IBM26BL486DX2-V80QP | 32-BIT, 80 MHz, MICROPROCESSOR, PQFP208 |
| IBM26BL486DX2-V50GP | 32-BIT, 50 MHz, MICROPROCESSOR, CPGA168 |
| IBM26BL486DX2-V50QP | 32-BIT, 50 MHz, MICROPROCESSOR, PQFP208 |
| IBM26BL486DX2-66GP | 32-BIT, 66 MHz, MICROPROCESSOR, CPGA168 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25PPC970MP7TR23AET | 制造商:IBM 功能描述:ANTARES MP DD1.1X 1.8GHZ PERFORMANCE OPTIMIZED - Trays |
| IBM25PPC970MP7TR30AET | 制造商:IBM Microelectronics 功能描述:ANTARES MP DD1.1X 2.0GHZ PERFORMANCE OPTIMIZED - Trays |
| IBM25PPC970MP7TR40AET | 制造商:IBM 功能描述:ANTARES MP DD1.1X 2.5GHZ PERFORMANCE OPTIMIZED - Trays |
| IBM25PPC970MP7TR50AET | 制造商:IBM 功能描述:ANTARES MP DD1.1X 1.2GHZ POWER OPTIMIZED - Trays |
| IBM25PPC970MP7TR60AET | 制造商:IBM 功能描述:ANTARES MP DD1.1X 1.4GHZ POWER OPTIMIZED - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。