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| 型號： | IBM25PPC970MP7TR21AFT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1600 MHz, RISC PROCESSOR, CBGA575 |
| 封裝： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-575 |
| 文件頁數(shù)： | 32/74頁 |
| 文件大?。?/td> | 845K |
| 代理商： | IBM25PPC970MP7TR21AFT |
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Datasheet
PowerPC 970MP RISC Microprocessor
Electrical and Thermal Characteristics
Page 38 of 74
Version 1.3
January 17, 2008
Figure 3-8. CP0_HRESET and BYPASS Timing Diagram
Notes:
1. These timings refer to the following pins: BUS_CFG(0:2) and PROCID(0:1).
2. These timings refer to the following pins: CKTERM_DIS, PLL_MULT, and PLL_RANGE(1:0).
These pins can only be changed by driving CP0_HRESET and BYPASS low.
3. CP0_HRESET and BYPASS might be low during initial program load (IPL) stages and not have to transition power before reference
time A.
4. PLL control inputs must not change while CP0_HRESET is low.
5. The legend for this figure is provided in Table 3-21 on page 37.
Table 3-22. Mode Select Type Input Signals
Pin Name
Description
Comment
Pin Location
BUS_CFG(0:2)
Bus configuration
Select core clock to bus clock ratio.
A11, D12, B11
CKTERM_DIS
Clock receiver termination
Disables the 50
Ω parallel SYSCLK termination.
Pulled up to OVDD for applications using external ter-
mination on SYSCLK and SYSCLK. Otherwise,
pulled low to GND.
Y5
PLL_MULT
Select between multiplier 8 or 12
AC5
PLL_RANGE(1:0)
PLL range select
AD3, AA4
PROCID(0:1)
Processor identifier (ID)
For use in a multiprocessor environment.
N21, N22
PLL stable
CP0_HRESET
Power
PLL_LOCK
>1 ms
200
μs
800
μs
BYPASS
SYSCLK ramp up completed
800
μs
4
3
6
5
PLL Control Inputs2
Mode Select Inputs1
All power supply voltages stable and
Reference
Time A
1
2
CP0_SRESET
100
μs
500
μs
>100 ns before INITCORE
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