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參數(shù)資料
| 型號： | IBM25PPC970MP7TR21AFT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1600 MHz, RISC PROCESSOR, CBGA575 |
| 封裝： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-575 |
| 文件頁數(shù)： | 48/74頁 |
| 文件大?。?/td> | 845K |
| 代理商： | IBM25PPC970MP7TR21AFT |
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Datasheet
PowerPC 970MP RISC Microprocessor
Dimensions and Physical Signal Assignments
Page 52 of 74
Version 1.3
January 17, 2008
CP0_INT
AB13
Low
Input
—
CP0_KELV_GND0
W2
—
GND
Test Points
CP0_KELV_V0
AB4
—
VDD
Test Points
CP0_PSRO0
V3
—
Output
—
CP0_QACK
AD21
Low
Input
—
CP0_QREQ
AB9
Low
Output
—
CP0_SRESET
AB7
Low
Input
—
CP1_DIODE_NEG
AC24
—
CP1_DIODE_POS
AB24
—
CP1_FRED_EN
AD17
High
Input
—
CP1_FRED_GND
Y12
—
GND
—
CP1_HRESET
AC16
Low
Input
—
CP1_INT
AD20
Low
Input
—
CP1_KELV_GND1
W22
—
GND
Test Points
CP1_KELV_V1
W21
—
VDD
Test Points
CP1_QACK
AD18
Low
Input
—
CP1_QREQ
AC21
Low
Output
—
CP1_SRESET
AB22
Low
Input
—
DI2
R24
Low
Input
—
EI_DISABLE
B12
High
Input
—
Table 4-4. Pinout Listing for the CBGA Package (Page 2 of 6)
Signal Name
Pin Number
Active
I/O
PI/PO1
Notes
Notes:
1. PI = processor input, PO= processor output, BiDi = bidirectional, OD = open drain. For additional information, see Section 3.5 Pro-
cessor Interconnect Specifications on page 30.
2. The PLL_MULT and PLL_RANGE (1:0) bits can be overwritten by the JTAG commands, and the BUS_CFG bits can be changed by
scan communication (SCOM) commands during the power-on reset (POR) sequence. See the PowerPC 970MP Power-On Reset
Application Note for more details.
3. These pins should be used as regulator references and also to measure on-chip voltage drop and noise. They must not be con-
nected to the GND and VDD planes. See Section 5.4.1 Using the Kelvin Voltage and Ground Pins on page 61 and Table 3-2 Maxi-
mum Allowable Current on Kelvin Probe Pins (DD1.1x) on page 23 for more details.
4. For correct operation, this pin must be tied to GND. See Table 5-8 PowerPC 970MP Pins for Manufacturing Test Only on page 65.
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