參數(shù)資料
型號(hào)： IBM25PPC970MP7TR21AFT
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 1600 MHz, RISC PROCESSOR, CBGA575
封裝： 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-575
文件頁數(shù)： 29/74頁
文件大?。?/td> 845K
代理商： IBM25PPC970MP7TR21AFT
Datasheet
PowerPC 970MP RISC Microprocessor
Version 1.3
January 17, 2008
Electrical and Thermal Characteristics
Page 35 of 74
3.6.1 TBEN Input Pin
The TBEN input pin can be used as either an enable for the internal timebase/decrementer or as an external
clock input. The mode is controlled by setting bit 19 of Hardware Implementation Dependent Register 0
(HID0[19]). When this bit is ‘0’, the timebase and decrementer update at 1/16th the processor core frequency
whenever TBEN is pulled up to OVDD (traditional enable mode for the internal timebase/decrementer). When
HID0[19] is ‘1’, the timebase and decrementer are clocked by the rising edge of TBEN (external clock input
mode). When the external clock input mode is used, the TBEN input frequency must not exceed 1/16th of the
core processor maximum frequency.
Figure 3-7. Asynchronous Input Timing
ALL ACTIVE
3
1
2
LOW INPUTS
VM
ALL ACTIVE
3
1
2
HIGH INPUTS
VM
Notes:
1. No reference to SYSCLK because these inputs are sampled using the internal core clock.
2. Define minimal pulse width as > 1 ns.
3. Define maximum rise and fall times as < 1ns.
4. VM = midpoint voltage (OVDD/2).
5. These timings refer to the following pins: CP0_INT, CP1_INT, MCP, CP0_QACK, CP1_QACK, CP0_SRESET, CP1_SRESET,
CP0_HRESET, CP1_HRESET, and TBEN.
6. The legend for this figure is provided in Table 3-15 on page 34, Table 3-16 on page 34 and Table 3-17 on page 34.
7. Rise and fall times are specified from 20% to 80%.
All active
3
1
2
low inputs
VM
All active
3
2
high inputs
VM
3
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