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| 型號： | IBM25PPC970MP7TR21AFT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1600 MHz, RISC PROCESSOR, CBGA575 |
| 封裝： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-575 |
| 文件頁數(shù)： | 18/74頁 |
| 文件大?。?/td> | 845K |
| 代理商： | IBM25PPC970MP7TR21AFT |
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Datasheet
PowerPC 970MP RISC Microprocessor
Version 1.3
January 17, 2008
Page 25 of 74
3.1.4 dc Electrical Specifications
Table 3-5. dc Electrical Specifications
Characteristic
Symbol
Voltage
Unit
Notes
Minimum
Maximum
SYSCLK, SYSCLK input high voltage
—
0.7
× OV
DD
OVDD + 0.3
V
SYSCLK, SYSCLK input low voltage
—
-0.3
0.3
× OV
DD
Processor interface (PI) input high voltage
VIH
(0.5
× OV
DD) + 0.2
—
V
PI input low voltage
VIL
—
(0.5
× OV
DD) - 0.2
V
NonPI input high voltage
VIH
0.7
× OV
DD
—V
NonPI input low voltage
VIL
—0.3
× OV
DD
PI output high voltage
VOH
0.78
× OV
DD
—V
PI output low voltage
VOL
—
0.22
× OV
DD
NonPI output high voltage, IOH = -2 mA
VOH
OVDD - 0.2
—
V
—
NonPI output low voltage, IOL = 2 mA
VOL
—0.2
V
—
Open-drain (OD) output low, IOL = 2 mA (CHKSTOP, I2CGO)
VOL
—0.2
V
OD output low, IOL = 5 mA (I
2C)
VOL
—0.2
V
—
Input leakage current, VIN = OVDD and VIN = 0 V
IIN
—60
μA—
Hi-Z (off state) leakage current, VOUT = OVDD and VOUT = 0 V
ITSO
—60
μA—
Input capacitance, VIN = 0 V, f = 1 MHz
CIN
—5.0
pF
Notes:
1. The SYSCLK differential receiver requires a high-speed transceiver logic (HSTL) differential signaling level. See the Joint Electron
Device Engineering Council (JEDEC) HSTL standard.
2. See Section 3.5 Processor Interconnect Specifications on page 30. Minimum input must meet the eye opening requirements of the
link.
3. The Joint Test Action Group (JTAG) signals TDI, TMS, and TRST do not have internal pullups; therefore, a pullup must be added to
the system board. Pullups should be added and adjusted according to the system implementation. These input and outputs meet
the dc specification in the JEDEC standard JESD8-11 for the 1.5 V normal power supply range.
4. A 100
Ω split terminator is the test load. Note that a 40 Ω driver has an up level of 0.78 × OV
DD for VOH and 0.22 × OVDD at VOL.
See Section 3.5 Processor Interconnect Specifications on page 30 for information about other drivers.
5. There are two open-drain signals that use this type of driver: CHKSTOP and I2CGO. The pullup for these nets depends on the rise
time requirement, net load, and topology. The following examples are two bounding suggestions based on a point-to-point 50
Ω net
with two lengths (5 cm and 61 cm). A 33
Ω series source terminator was added in both runs.
Examples:
500
Ω pullup dc low level 0.18 V at the receiver
Trise 0.2 V - 0.8 V = 55 ns at 61 cm
Trise 0.2 V - 0.8 V = 10 ns at 5 cm
1k
Ω pullup dc low level 0.13 V at the receiver
Trise 0.2 V - 0.8 V = 115 ns at 61 cm
Trise 0.2 V - 0.8 V = 20 ns at 5 cm
6. Capacitance values are guaranteed by design and characterization, and are not tested.
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