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| 型號： | IBM25PPC970MP7TR21AFT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1600 MHz, RISC PROCESSOR, CBGA575 |
| 封裝： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-575 |
| 文件頁數(shù)： | 47/74頁 |
| 文件大?。?/td> | 845K |
| 代理商： | IBM25PPC970MP7TR21AFT |
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Datasheet
PowerPC 970MP RISC Microprocessor
Version 1.3
January 17, 2008
Dimensions and Physical Signal Assignments
Page 51 of 74
4.3 PowerPC 970MP Microprocessor Pinout Listings
Table 4-4 provides the pinout listing for the CBGA package.
Table 4-4. Pinout Listing for the CBGA Package (Page 1 of 6)
Signal Name
Pin Number
Active
I/O
Notes
ADIN(0:43)
H23, G23, J24, H22, B14, A15, K22, J23, L24, E22, D23,
E24, A23, G24, F23, D15, B15, A16, E15, C16, C21, E21,
C22, D21, B22, B23, A18, D18, C14, E16, E17, E20, E19,
C20, C19, D17, B20, A21, A19, B18, C15, A17, C17, C18
—
Processor Input
—
ADOUT(0:43)
N2, G3, J2, L2, M2, K3, K2, H3, J1, E3, F1, D3, E1, F3,
C7, E10, D10, B9, E9, B8, B2, E5, A2, E7, A4, C3, C1, C6,
C10, A9, B5, D4, E4, C5, A6, D7, D6, B4, A8, E8, C9, D9,
A7, B6
—
Processor Output
—
ANALOG_GND
A13
—
Analog GND
—
ATTENTION
AC7
High
Output
—
AVDD
A12
—
Analog VDD
—
AVP_RESET
U24
Low
Input
—
BI_MODE
AD24
Low
Input
—
BUS_CFG(0:2)
A11, D12, B11
—
Input
BYPASS
T24
Low
Input
—
C1_UND_GLOBAL
AB17
High
Input
—
C2_UND_GLOBAL
AB15
High
Input
—
CHKSTOP
T22
Low
OD
BiDi
—
CKTERM_DIS
Y5
High
Input
—
CLKIN
C24
—
Processor Input
—
CLKIN
B24
—
Processor Input
—
CLKOUT
D2
—
Processor Output
—
CLKOUT
D1
—
Processor Output
—
CP0_DIODE_NEG
Y4
—
CP0_DIODE_POS
Y3
—
CP0_FRED_EN
Y11
High
Input
—
CP0_FRED_GND
AC12
—
GND
—
CP0_HRESET
AA9
Low
Input
—
Notes:
1. PI = processor input, PO= processor output, BiDi = bidirectional, OD = open drain. For additional information, see Section 3.5 Pro-
2. The PLL_MULT and PLL_RANGE (1:0) bits can be overwritten by the JTAG commands, and the BUS_CFG bits can be changed by
scan communication (SCOM) commands during the power-on reset (POR) sequence. See the PowerPC 970MP Power-On Reset
Application Note for more details.
3. These pins should be used as regulator references and also to measure on-chip voltage drop and noise. They must not be con-
nected to the GND and VDD planes. See Section 5.4.1 Using the Kelvin Voltage and Ground Pins on page 61 and Table 3-2 Maxi-
mum Allowable Current on Kelvin Probe Pins (DD1.1x) on page 23 for more details.
4. For correct operation, this pin must be tied to GND. See Table 5-8 PowerPC 970MP Pins for Manufacturing Test Only on page 65.
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