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參數(shù)資料
| 型號(hào)： | IBM25PPC970MP7TR21AFT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1600 MHz, RISC PROCESSOR, CBGA575 |
| 封裝： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-575 |
| 文件頁數(shù)： | 49/74頁 |
| 文件大?。?/td> | 845K |
| 代理商： | IBM25PPC970MP7TR21AFT |
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Datasheet
PowerPC 970MP RISC Microprocessor
Version 1.3
January 17, 2008
Dimensions and Physical Signal Assignments
Page 53 of 74
GND
A5, A14, A20, A22
B1, B3, B10, B17
C8, C23
D5, D11, D14, D20
E2, E18, E23
F7, F11, F13, F15, F20, F21, F24
G2, G4, G5, G6, G8, G10, G12, G16, G18
H2, H4, H7, H9, H11, H13, H15, H17, H19, H21
J4, J6, J8, J10, J12, J14, J16, J18, J20, J22
K1, K4, K7, K9, K11, K13, K15, K17, K19, K21, K24
L3, L6, L8, L10, L12, L14, L16, L18, L22
M5, M7, M9, M11, M13, M15, M17, M19, M21
N3, N4, N6, N8, N10, N12, N14, N16, N18, N20
P2, P5, P7, P9, P11, P13, P15, P17, P19, P21, P23, P24
R1, R4, R6, R8, R10, R12, R14, R16, R18, R20, R23
T5, T7, T9, T11, T13, T15, T17, T19, T21
U4, U6, U8, U10, U12, U14, U16, U18, U20
V5, V7, V9, V11, V13, V15, V17, V19, V21, V23
W1, W3, W6, W8, W10, W12, W16, W18, W20
Y7, Y9, Y13, Y15, Y17, Y19, Y22
AA1, AA2, AA6, AA8, AA10, AA12, AA14, AA16, AA18,
AA20, AA24
AB2, AB5, AB19
AC1, AC8, AC10, AC11, AC18, AC22
AD2, AD5, AD12, AD14, AD16, AD19, AD23
—GND
—
GPULDBG
Y24
High
Input
—
I2CCK
V24
—
OD
BiDi
—
I2CDT
V22
—
OD
BiDi
—
I2CGO
E13
—
OD
—
I2CSEL
U1
High
Input
KELV_GND2
B13
—
GND
Test Points
KELV_OVDD
A10
—
OVDD
Test Points
LSSDMODE
U2
High
Input
—
LSSD_RAMSTOP_ENABLE
T2
High
Input
—
Table 4-4. Pinout Listing for the CBGA Package (Page 3 of 6)
Signal Name
Pin Number
Active
I/O
PI/PO1
Notes
Notes:
1. PI = processor input, PO= processor output, BiDi = bidirectional, OD = open drain. For additional information, see Section 3.5 Pro-
cessor Interconnect Specifications on page 30.
2. The PLL_MULT and PLL_RANGE (1:0) bits can be overwritten by the JTAG commands, and the BUS_CFG bits can be changed by
scan communication (SCOM) commands during the power-on reset (POR) sequence. See the PowerPC 970MP Power-On Reset
Application Note for more details.
3. These pins should be used as regulator references and also to measure on-chip voltage drop and noise. They must not be con-
nected to the GND and VDD planes. See Section 5.4.1 Using the Kelvin Voltage and Ground Pins on page 61 and Table 3-2 Maxi-
mum Allowable Current on Kelvin Probe Pins (DD1.1x) on page 23 for more details.
4. For correct operation, this pin must be tied to GND. See Table 5-8 PowerPC 970MP Pins for Manufacturing Test Only on page 65.
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