參數(shù)資料
型號(hào)： IBM25PPC970MP7TR21AFT
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 1600 MHz, RISC PROCESSOR, CBGA575
封裝： 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-575
文件頁(yè)數(shù)： 36/74頁(yè)
文件大?。?/td> 845K
代理商： IBM25PPC970MP7TR21AFT
Datasheet
PowerPC 970MP RISC Microprocessor
Version 1.3
January 17, 2008
Electrical and Thermal Characteristics
Page 41 of 74
3.10 I2C and JTAG
The single external I2C interface connects to two I2C controllers, one for each processing unit. The controllers
are distinguished by the low-order address bit, which is ‘0’ for processing unit 0 and ‘1’ for processing unit 1.
Similarly, the single external JTAG interface connects to two daisy-chained JTAG controllers, one for each
processing unit.
3.10.1 I2C Bus Timing Information
The I2C bus specification can be downloaded from NXP Web site at http://www.nxp.com/prod-
The PowerPC 970MP I2C bus conforms to the standard-mode timing specification and does not support the
high-speed (Hs-mode) or fast-mode timing. The default I2C bus speed for the PowerPC 970MP is 50 kHz. A
scan communication (SCOM) write with the I2C bus running at 50 kHz is needed to allow the bus to conform
to the standard-mode timing specification of 100 kHz. See the PowerPC 970MP Power-On Reset Application
Note for more details.
The PowerPC 970MP I2C pins are limited to OVDD voltages. Level shifting or pullups or both might be
required to interface to higher voltage devices. See The I2C bus specification for recommendations on level
shifting and pullups.
Notes:
1. To avoid problems, level shifted PPC970MP I2C bus pins must not be wired together with non-PowerPC
970MP parts in a system. The PowerPC 970MP should have its own private level shifter.
2. If one level shifter is used for multiple PowerPC 970MP microprocessors, the length of the traces must be
controlled very carefully.
3.10.2 JTAG ac Timing Specifications
1149.1) ac timing specifications as defined in Figure 3-10 JTAG Clock Input Timing Diagram on page 42 and
Figure 3-11 Test Access Port Timing Diagram on page 43. The five JTAG signals are as follows:
1. TDI (test data in)
2. TDO (test data out)
3. TMS (test mode select)
4. TCK (test clock)
5. TRST (test reset)
Note: The PowerPC 970MP diverges from the standard IEEE ac timing implementation in this regard:
JTAG is normally used with the PLL running; however, it can also be used with the PLL in bypass
mode. If the PLL is in bypass mode, clock pulses must be supplied to the SYSCLK and SYSCLK pins
at a rate 40 times higher than the TCK rate.
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參數(shù)描述
IBM25PPC970MP7TR23AET 制造商:IBM 功能描述:ANTARES MP DD1.1X 1.8GHZ PERFORMANCE OPTIMIZED - Trays
IBM25PPC970MP7TR30AET 制造商:IBM Microelectronics 功能描述:ANTARES MP DD1.1X 2.0GHZ PERFORMANCE OPTIMIZED - Trays
IBM25PPC970MP7TR40AET 制造商:IBM 功能描述:ANTARES MP DD1.1X 2.5GHZ PERFORMANCE OPTIMIZED - Trays
IBM25PPC970MP7TR50AET 制造商:IBM 功能描述:ANTARES MP DD1.1X 1.2GHZ POWER OPTIMIZED - Trays
IBM25PPC970MP7TR60AET 制造商:IBM 功能描述:ANTARES MP DD1.1X 1.4GHZ POWER OPTIMIZED - Trays
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