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| 型號(hào)： | IBM25PPC970MP7TR21AFT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1600 MHz, RISC PROCESSOR, CBGA575 |
| 封裝： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-575 |
| 文件頁(yè)數(shù)： | 38/74頁(yè) |
| 文件大?。?/td> | 845K |
| 代理商： | IBM25PPC970MP7TR21AFT |
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Datasheet
PowerPC 970MP RISC Microprocessor
Version 1.3
January 17, 2008
Electrical and Thermal Characteristics
Page 43 of 74
Figure 3-11 provides the test access port timing diagram.
3.10.3 I2C and JTAG Considerations
The PowerPC 970MP supports I2C and JTAG. The I2C data and clock pins as well as the TCK, TMS, TDI,
and TRST pins should be pulled up to OVDD. Use of the I
2C or JTAG bus is mutually exclusive and controlled
by the I2CSEL pin. If this pin is high, the I2C bus can be used. If the pin is low, the JTAG bus can be used.
Traffic on the nonselected bus (I2C or JTAG depending on I2CSEL) is ignored and does not have any side
effect.
3.10.3.1 Guidance for Using Both I2C and JTAG
If selective use of both interfaces is required, then the I2CSEL pin can be switched while the system is
running. For correct operation, it is recommended to switch the I2CSEL pin only while no traffic is active on
either interface to prevent misrecognition of a partial transmission. To ease this operation in debug mode
(GPULDBG = ‘1’), the I2CGO pin can be monitored or directly connected to the I2CSEL pin. This pin will
switch from ‘0’ to ‘1’ whenever it is safe to switch I2CSEL from ‘0’ to ‘1’ for I2C usage. Similarly, it will switch
from ‘1’ to ‘0’ whenever it is safe to switch I2CSEL from ‘1’ to ‘0’ for JTAG usage. See the PowerPC 970MP
Power-On Reset Application Note for a description of how the I2CGO pin is controlled by software.
3.10.4 Boundary Scan Considerations
The PowerPC 970MP does not support the boundary scan description language (BSDL) standard for imple-
menting boundary scan testing. Boundary scan patterns are available for customer use, but require other
signals to be controlled in addition to the JTAG port. Boundary scan testing requires an input clock (SYSCLK
and SYSCLK) and control of CP0_HRESET.
Figure 3-11. Test Access Port Timing Diagram
Note: The legend for this figure is provided in Table 3-24 JTAG ac Timing Specifications (Dependent on SYSCLK) on page 42.
6
4
5
TCK
TDI, TMS
TDO
Input Data (Valid)
Output Data (Valid)
TDO
7
8
Output Data (Invalid)
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| IBM25PPC970MP7TR23AET | 制造商:IBM 功能描述:ANTARES MP DD1.1X 1.8GHZ PERFORMANCE OPTIMIZED - Trays |
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