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參數(shù)資料
| 型號： | IBM25PPC970MP7TR21AFT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1600 MHz, RISC PROCESSOR, CBGA575 |
| 封裝： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-575 |
| 文件頁數(shù)： | 50/74頁 |
| 文件大?。?/td> | 845K |
| 代理商： | IBM25PPC970MP7TR21AFT |
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Datasheet
PowerPC 970MP RISC Microprocessor
Dimensions and Physical Signal Assignments
Page 54 of 74
Version 1.3
January 17, 2008
LSSD_SCAN_ENABLE
U22
High
Input
—
LSSD_STOP_ENABLE
AC14
High
Input
—
LSSD_STOPC2_ENABLE
AB11
High
Input
—
LSSD_STOP_C2STAR_ENABLE U3
High
Input
—
MASTERSEL
R2
—
Input
—
MCP
AA21
Low
Input
—
PLL_LOCK
U23
High
Output
—
PLL_MULT
AC5
—
Input
PLL_RANGE(1:0)
AD3, AA4
—
Input
PLLTEST
D13
High
Input
—
PLLTESTOUT
C12
—
Output
—
PROCID(0:1)
N21, N22
—
Input
—
PSRO_ENABLE
Y21
—
Input
—
PSYNC
P4
—
Input
—
PULSE_SEL(0:2)
V1, T3, AD10
—
Input
—
RI
W4
Low
Input
—
SPARE1
AD6
—
Input/Output
SPARE2
AC3
—
Input/Output
SRIN(0:1)
N24, K23
—
Processor Input
—
SRIN(0:1)
M24, L23
—
Processor Input
—
SROUT(0:1)
M1, H1
—
Processor Output
—
SROUT(0:1)
L1, G1
—
Processor Output
—
SYNC_ENABLE
W24
Low
Input
—
SYSCLK
F12
—
Input
—
SYSCLK
E12
—
Input
—
TBEN
AD15
High
Input
—
TCK
AB23
—
Input
—
TDI
AA23
—
Input
—
TDO
AD8
—
Output
—
Table 4-4. Pinout Listing for the CBGA Package (Page 4 of 6)
Signal Name
Pin Number
Active
I/O
PI/PO1
Notes
Notes:
1. PI = processor input, PO= processor output, BiDi = bidirectional, OD = open drain. For additional information, see Section 3.5 Pro-
cessor Interconnect Specifications on page 30.
2. The PLL_MULT and PLL_RANGE (1:0) bits can be overwritten by the JTAG commands, and the BUS_CFG bits can be changed by
scan communication (SCOM) commands during the power-on reset (POR) sequence. See the PowerPC 970MP Power-On Reset
Application Note for more details.
3. These pins should be used as regulator references and also to measure on-chip voltage drop and noise. They must not be con-
nected to the GND and VDD planes. See Section 5.4.1 Using the Kelvin Voltage and Ground Pins on page 61 and Table 3-2 Maxi-
mum Allowable Current on Kelvin Probe Pins (DD1.1x) on page 23 for more details.
4. For correct operation, this pin must be tied to GND. See Table 5-8 PowerPC 970MP Pins for Manufacturing Test Only on page 65.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IBM25PPC970MP7TR23AET | 制造商:IBM 功能描述:ANTARES MP DD1.1X 1.8GHZ PERFORMANCE OPTIMIZED - Trays |
| IBM25PPC970MP7TR30AET | 制造商:IBM Microelectronics 功能描述:ANTARES MP DD1.1X 2.0GHZ PERFORMANCE OPTIMIZED - Trays |
| IBM25PPC970MP7TR40AET | 制造商:IBM 功能描述:ANTARES MP DD1.1X 2.5GHZ PERFORMANCE OPTIMIZED - Trays |
| IBM25PPC970MP7TR50AET | 制造商:IBM 功能描述:ANTARES MP DD1.1X 1.2GHZ POWER OPTIMIZED - Trays |
| IBM25PPC970MP7TR60AET | 制造商:IBM 功能描述:ANTARES MP DD1.1X 1.4GHZ POWER OPTIMIZED - Trays |
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