參數(shù)資料
型號: CR16MHS9VJEE
廠商: National Semiconductor Corporation
元件分類: 16位微控制器
英文描述: Family of CompactRISC 16-Bit Microcontrollers
中文描述: 家庭CompactRISC 16位微控制器
文件頁數(shù): 97/99頁
文件大?。?/td> 449K
代理商: CR16MHS9VJEE
97
www.national.com
22.0 Appendix
22.1
8-BIT MICROWIRE/SPI (MWSPI)
22.1.1
According to the specification, the MSKn clock output in mas-
ter mode should have the value of the MnIDL bit of the
MUnCTL1 register, even when the module is disabled. How-
ever, the MSKn pin will always be at low level, when the al-
ternate function of the MSKn pin is enabled and the module
is disabled. Thus, even if the MnIDL bit is set, the MSKn clock
will change to a low level as soon as the module is disabled.
If any slave is selected at this time, it will interpret this un-
wanted transition as a shift clock.
MWSPI Problem Description
22.1.2
Even if the module is disabled and the alternate function of
the MSKn pin is enabled, the module can still influence the
MSKn pin and drives the default value ‘0’.
MWSPI Problem Cause
22.1.3
When the MSKn idle level of ‘1’ is to be used, the following
procedure should be followed when the module is disabled:
1. Set the MSKn pin to high level in the corresponding port
data output register.
2. Configure the MSKn pin to an output in the correspond-
ing port direction register.
3. Disable the alternate function of the MSKn pin in the cor-
responding port alternate function register.
4. Disable the MWSPI module.
MWSPI Problem Solutions
22.2
TIMING AND WATCHDOG MODULE
22.2.1
Timing and WATCHDOG Module Problem
Description
The available window for a valid WATCHDOG service varies
with the TWM configuration and the operating mode of the
R16MHS9. Therefore it is not possible to generally provide
the limits for the maximum service window. However, the lim-
its for the minimum service window is guaranteed and should
be used.
22.2.2
Timing and WATCHDOG Module Problem
Cause
The timing and WATCHDOG module uses two different clock
signals for its operation, the slow system clock as well as the
fast system clock.
The slow system clock can either be generated by an exter-
nal 32 kHz quartz or it can be derived from the fast system
clock by means of a prescaler counter in the CLK2RES mod-
ules. The TWM can operate off a maximum slow system
clock of 100 kHz. The WATCHDOG counter (down-counter)
is either clocked directly by the slow system (T0IN) or it is
decremented every time the counter T0 underflows
(T0OUT).
The fast system clock is used for accesses to TWM registers,
which build the user interface of the TWM. These user inter-
face registers include all memory-mapped registers of the
TWM.
Every time the user (CR16B core) writes to a TWM configu-
ration register or to the WATCHDOG Service Data Match
register, this “high speed operation” must be synchronized to
the internal TWM logic running at the slow clock rate. This
synchronization process takes a variable number of low
speed clock cycles, depending on the ratio between the low-
speed and the high-speed system clock and the phase shift
between the two clock signals. The more the two frequencies
differ from each other, the longer it takes the synchronization
process.
In other words, write operations to the TWM registers take a
certain number of low-speed clock cycles to show the de-
sired effects to the TWM logic.
This fact is especially critical for the write operation for the
WATCHDOG service, as it affects the allowed window for a
valid WATCHDOG service.
If the device runs in active mode, the synchronization pro-
cess can take up to four WATCHDOG counter clock cycles.
This limits the available WATCHDOG service to the window
shown in Figure48:
Figure 48.
WATCHDOG Services Windows in Active Mode
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