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19.0 Memory Map
Please refer to individual datasheets for its own set of mem-
ory maps. The CompactRISC architecture supports a uni-
form linear address space of 2 megabytes. The device
implementation of this architecture uses only the lowest 64
kbytes of address space, ranging from 0000 to FFFF hex.
Table20 is a memory map showing the types of memory and
peripherals that occupy this memory space. Address ranges
not listed in the table are reserved and should not be read or
written.
Table 20
Device Memory Map
Table21 is a detailed memory map showing the specific
memory address of the memory, I/O ports, and registers. The
table shows the starting address, the size, and a brief de-
scription of each memory block and register. For detailed in-
formation on using these memory locations, see the
applicable sections in the data sheet.
All addresses not listed in the table are reserved and should
not be read or written. An attempt to access an unlisted ad-
dress will have unpredictable results.
Each byte-wide register occupies a single address and can
be accessed only in a byte-wide transaction. Each word-wide
register occupies two consecutive memory addresses and
can be accessed only in a word-wide transaction. Both the
byte-wide and word-wide registers reside at word boundaries
(even address). Thus, each byte-wide register uses only the
lowest eight bits of the internal data bus.
Most device registers are read/write registers. However,
some registers are read-only or write-only, as indicated in the
table. An attempt to read a write-only register or to write a
read-only register will have unpredictable results.
When the software writes to a register in which one or more
bits are reserved, it must write a zero to each reserved bit un-
less indicated otherwise in the description of the register.
Reading a reserved bit returns an undefined value.
Address
Range (hex)
Description
0000-BFFF
DA00-DFF7
DFF8-DFFF
E000-E7FF
F000-F27F
F900-F930
FB00-FB06
FB10-FB16
FC40-FC88
Flash Program Memory (48 kbytes)
ISP Memory (1.5 kbytes)
Program ROM control/status
Static RAM (2 kbytes)
EEPROM Data Memory (640 bytes)
Device configuration registers
Port B registers
Port C registers
Clock, Power Management, and Wake-up
registers
Port G registers
Port F registers
Interrupt registers
USART 1 registers
MICROWIRE registers
USART 2 registers
Port I registers
Port L registers
Timer and WATCHDOG registers
MFT1 Timer registers
MFT2 Timer registers
A/D Converter registers
a
Analog Comparator register
a
a
. 44 pin devices may not include this module
FCA0-FCA8
FD20-FD28
FE00-FE0C
FE40-FE4E
FE60-FE68
FE80-FE8E
FEE0-FEE8
FF00-FF08
FF20-FF2A
FF40-FF50
FF60-FF70
FFC0-FFD0
FFE0-FFE0