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參數(shù)資料
| 型號： | CR16MHS9VJEE |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 16位微控制器 |
| 英文描述： | Family of CompactRISC 16-Bit Microcontrollers |
| 中文描述： | 家庭CompactRISC 16位微控制器 |
| 文件頁數(shù)： | 19/99頁 |
| 文件大?。?/td> | 449K |
| 代理商： | CR16MHS9VJEE |
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7.0
Bus Interface Unit
The Bus Interface Unit (BIU) controls the interface between
the on-chip modules and the internal core bus. It determines
the configured parameters for bus access (such as the num-
ber of wait states for memory access) and issues the appro-
priate bus signals for the requested access.
7.1
There are four types of data transfer bus cycles:
Normal read
Fast read
Early write
Late write
Note:
For write operations, this device utilizes the Late write
operation.
The type of data cycle used in a particular transaction de-
pends on the type of CPU operation (a write or a read), the
type of memory or I/O being accessed, and the access type
programmed into the BIU control registers (early/late write or
normal/fast read).
For read operations, a basic normal read takes two clock cy-
cles, whereas a fast read bus cycle takes one clock cycle.
Upon reset of the device, normal read bus cycles are en-
abled by default.
For write operations, a basic late write bus cycle takes two
clock cycles, whereas a basic early write bus cycle takes
three clock cycles. Upon reset of the device, early write bus
cycles are enabled by default. However, late write bus cycles
are needed for ordinary write operations, so this configura-
tion should be changed by the application software (see
Section7.2.1).
In certain cases, one or more additional clock cycles are add-
ed to a bus access cycle. There are two types of additional
clock cycles for ordinary memory accesses, called internal
wait cycles (TIW) and hold (Thold) cycles.
A wait cycle is inserted in a bus cycle just after the memory
address has been placed on the address bus. This gives the
accessed memory more time to respond to the transaction
request. A hold cycle is inserted at the end of a bus cycle.
This holds the data on the data bus for an extended number
of clock cycles.
BUS CYCLES
7.2
BIU CONTROL REGISTERS
The BIU has a set of control registers that determine how
many wait cycles and hold cycles are to be used for access-
ing memory. Upon start-up of the device, these registers
should be programmed with appropriate values so that the
minimum allowable number of cycles is used. This number
varies with the clock frequency used.
There are two applicable BIU registers: the BIU Configura-
tion (BCFG) register and the Static Zone 0 Configuration
(SZCFG0) register. These registers control the bus cycle
configuration used for accessing the flash program memory.
Note:
A system configuration register called the Module
Configuration (MCFG) register controls the number of wait
cycles used for accessing the EEPROM data memory. This
register is described in Section4.2.
7.2.1
The BIU Configuration (BCFG) Register is a byte-wide, read/
write register that selects either early write or late write bus
cycles. The register address is F900 hex. Upon reset, the
register is initialized to 07 hex. The register format is shown
below.
7
6
5
4
3
2
Reserved
Note 1
BIU Configuration (BCFG) Register
EWR
Early Write. This bit is cleared to 0 for late write
operation (two clock cycles to write) or set to 1
for early write operation.
Note 1:
This bit (bit 1 or bit 2) controls the configuration of the
224-pin device used in emulation equipment. The CPU
should set this bit to 1 when it writes to the register.
Upon reset, the BCFG register is initialized to 07 hex, which
selects early write operation. However, late write operation is
required for normal device operation, so the software should
change the register value to 06 hex.
7.2.2
The I/O Zone Configuration (IOCFG) register is a word-wide,
read/write register that sets the timing and bus characteris-
tics of I/O Zone memory accesses. In the device implemen-
tation, the registers associated to Port B and Port C reside in
the I/O memory array. (These ports are used as a 16-bit data
port, if the device operates in development mode.)
The IOCFG register address is F902 hex. Upon reset, the
register is initialized to 069F hex. The register format is
shown below.
15
14
13
12
11
Reserved
I/O Zone Configuration (IOCFG) Register
WAIT
Memory Wait cycles
This field specifies the number of TIW (internal
wait state) clock cycles added for each memory
access, ranging from 000 binary for no addi-
tional TIW wait cycles to 111 binary for seven
additional TIW wait cycles. These bits are ig-
nored if the SZCFG0.FRE bit is set to 1.
Memory Hold cycles
This field specifies the number of Thold clock
cycles used for each memory access, ranging
from 00 binary for no Thold cycles to 11 binary
for three Thold clock cycles. These bits are ig-
nored if the SZCFG0.FRE bit is set to 1.
Bus Width
BW defines the external bus width for the I/O
zone. Bus width is initialized during reset to its
default value, which is 16 bits. If this bit is
cleared to 0 the external bus is 8 bits wide. To
set to external bus width to 16 bits, this bit has
to be set to 1. For the 80 pin package the Bus
width has to be set to 1. When using the device
in 224 pin package in emulator equipment the
HOLD
BW
1
0
Note 1
EWR
10
1
9
8
IPST
Reserved
7
6
Reserved
5
4
3
2
1
0
BW
HOLD
WAIT
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PDF描述 |
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| CR16MHS9VJEI | Family of CompactRISC 16-Bit Microcontrollers |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| CR16MHS9VJEI | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
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| CR16MNS544VC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
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