參數(shù)資料
型號(hào): CR16MHS9VJEE
廠商: National Semiconductor Corporation
元件分類: 16位微控制器
英文描述: Family of CompactRISC 16-Bit Microcontrollers
中文描述: 家庭CompactRISC 16位微控制器
文件頁(yè)數(shù): 24/99頁(yè)
文件大?。?/td> 449K
代理商: CR16MHS9VJEE
www.national.com
24
Programming Procedure
Programming is done by writing to all the words within a row,
one word following another sequentially, within a single high-
voltage pulse for the entire row. It is not possible to program
single bytes. Programming should be done only on erased
rows.
Programming a row requires the following code sequence:
1. Verify that the MSTAT.PGMBUSY bit is cleared.
2. Disable any enabled interrupts.
3. Write the proper key value to the PGMKEY register.
4. Write the desired word to the lowest address of the row.
5. Wait until the FLCSR.PMLFULL bit is cleared to 0.
6. Write the proper key value to the PGMKEY register.
7. Write the desired word to the next address of the row.
8. Repeat Steps 5, 6, and 7 until the whole row is written.
9. Re-enable any interrupts disabled in Step 2.
The programmed values can be verified by normal read op-
erations from the applicable memory locations.
Each time you write a word to the flash program memory us-
ing the procedure just described, the data word is stored in a
two-level write-data buffer. The first word written while the
program memory is idle starts the write cycle. Due to double-
buffering of the write path, a second word can be written to
the program memory while the first word is still being pro-
grammed. Writing the second word sets the FLCSR.PML-
FULL flag, thus indicating that the write-data buffer is full.
When programming of the first word is done, the memory ad-
dress is incremented, programming of the second word
starts, and the PLCSR.PMFULL flag is cleared. The next
word can then be written to the write-data buffer. This pro-
cess is repeated until there are no more words in the buffer
or the entire row has been programmed. All of this happens
within the same high-voltage programming pulse.
If a reset occurs in the middle of an erase or programming
operation, the operation is terminated. The reset is extended
until the flash memory returns to the idle state.
8.1.5
The internal hardware of the device handles the timing of
erase and programming operations. To drive the timing con-
trol circuits, the device divides the system clock by a pro-
grammable prescaler factor. You should select a prescaler
value to produce a program/erase clock of 200 kHz (or as
close as possible to 200 kHz without exceeding 200 kHz).
For the timing control circuit to operate correctly, you must
program the prescaler value in advance and leave it un-
changed while a program or erase operation is in progress.
A similar (but separate) prescaler factor is applied to the EE-
PROM data memory. See Section8.1.7 and Section8.3.4 for
details.
Erase and Programming Timing
8.1.6
Flash Program Memory Control and Status
Register (FLCSR)
The Flash Program Memory Control and Status (FLCSR)
register is a byte-wide, read/write register that contains sev-
eral status and control bits related to the program memory.
Upon reset, this register is cleared to zero when the flash
memory on the chip is in the idle state.
The register format is shown below.
7
6
5
4
ERASE
Erase Flash Program Memory Page. When set
(1), a write to the program memory erases the
whole page containing the addressed memory
location. When cleared (0), a write to the pro-
gram memory either has no effect on program-
ming the memory word (if properly set up for
programming). This bit should be changed only
when the flash memory is not busy being pro-
grammed or erased.
Program Memory Busy. This bit is automatical-
ly set to 1 when the flash program memory is
busy being programmed, and cleared to 0 at all
other times. (The MSTAT.PGMBUSY is also set
to 1 whenever the PMBUSY bit is set to 1.)
Program Memory Write-Latch Buffer Full.
When set (1), the double-buffered data register
for program memory write operations is full.
When cleared (0), the double-buffered data
register is not full.
Interrupt Enable for Program Memory Write.
When set (1), the flash program memory write
mechanism generates an interrupt whenever
the PMLFULL bit changes from 1 to 0. This is a
signal to the CPU to write the next word for pro-
gramming. When IENPROG is cleared, no
such interrupt is generated.
PMBUSY
PMLFULL
IENPROG
8.1.7
Program Memory Timing Prescaler Register
(FLPSLR)
The FLPSLR register is a byte-wide, read/write register that
selects the prescaler divider ratio for the flash program mem-
ory programming clock. Before you program or erase the pro-
gram memory for the first time, you should program the
FLPSLR register with the proper prescaler value, an 8-bit val-
ue called FTDIV. The device divides the system clock by (FT-
DIV+1) to produce the program memory programming clock.
You should choose a value of FTDIV to produce a clock of the
highest possible frequency that is equal to or just less than
200 kHz. For example, if the system clock frequency is 12.5
MHz, use the value 3E hex (62 decimal) for FTDIV, because
12.5 MHz / (62+1) = 198.4 kHz. Do not modify this register
while a flash program or erase operation is in progress.
Upon reset, this register is programmed by default with the
value 33 hex (51 decimal), which is an appropriate setting for
a 10.4 MHz system clock.
8.1.8
The PGMKEY register is a byte-wide, write-only register that
must be written with a key value (A3 hex) immediately prior
to each write to the flash program memory. Otherwise, the
write operation to the program memory will fail. This feature
is intended to prevent unintentional programming of the pro-
gram memory.
Reading this register always returns FF hex.
Program Memory Write Key Register (PGMKEY)
3
2
1
0
Reserved
IENPROG
PMLFULL
PMBUSY
ERASE
Reserved
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