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參數(shù)資料
| 型號： | CR16MHS9VJEE |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 16位微控制器 |
| 英文描述： | Family of CompactRISC 16-Bit Microcontrollers |
| 中文描述： | 家庭CompactRISC 16位微控制器 |
| 文件頁數(shù)： | 31/99頁 |
| 文件大?。?/td> | 449K |
| 代理商： | CR16MHS9VJEE |
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9.4.1
Non-Maskable Interrupt Status Register
(NMISTAT)
The NMISTAT register is a byte-wide, read-only register that
holds the current pending status of the Non-Maskable Inter-
rupt (NMI). This register is cleared upon reset. It is also
cleared each time it is read. The register format is shown be-
low.
7
6
5
4
3
Reserved
EXT
External Non-Maskable Interrupt Request.
When set to 1 by the hardware, it indicates an
external Non-Maskable Interrupt request has
occurred. See the description of the EXNMI
register below for more information.
9.4.2
The EXNMI register is a byte-wide, read/write register that
shows the current state of the NMI pin and also allows the
NMI trap to be enabled by setting either the EN bit or the EN-
LCK bit. Both of these bits are cleared upon reset. When the
software writes to this register, it must write 0 to all reserved
bit positions for the device to function properly. The register
format is shown below.
7
6
5
4
Reserved
External NMI Control/Status Register (EXNMI)
EN
Enable NMI Trap. When set to 1, NMI traps are
enabled and falling edge on the NMI pin gener-
ates a NMI trap. Each occurrence of an NMI
trap automatically clears the EN bit. The trap
service routine should set the EN bit to 1 before
returning control to the interrupted program.
When EN is cleared to 0, NMI traps are dis-
abled unless they are enabled with the ENLCK
bit. When the ENLCK bit is set to 1, the EN bit
is ignored.
NMI Pin. This bit shows the current state of the
NMI input pin (without logical inversion). A 1 in-
dicates a high level and a 0 indicates a low lev-
el on the pin. This is a read-only bit. In a write
operation, the value written to this bit position is
ignored.
Enable and Lock NMI Trap. When set to 1, NMI
traps are enabled and locked in the enabled
state. Each falling edge on the NMI pin gener-
ates a NMI trap, even if a previous NMI trap
has occurred and is still being processed.
When ENLCK is cleared to 0, NMI traps are
disabled unless they are enabled with the EN
bit.
PIN
ENLCK
9.4.3
The IVCT register is a byte-wide, read-only register that con-
tains the encoded value of the enabled and pending
maskable interrupt with the highest priority. The on-chip
hardware automatically updates this field whenever there is
a change in the highest-priority enabled and pending
maskable interrupt. The CPU reads this register during an in-
terrupt acknowledge core bus cycle to determine where to
begin executing the interrupt service routine. The register
Interrupt Vector Register (IVCT)
contents are guaranteed to be valid at that time. The register
is not guaranteed to contain valid data during a hardware up-
date operation. The register format is shown below.
7
6
5
4
0
0
0
INTVECT
Interrupt Vector. This 5-bit field contains the en-
coded value of the enabled and pending
maskable interrupt with the highest priority. For
example, if interrupts IRQ1 and IRQ6 are both
enabled and pending, the higher-priority inter-
rupt is IRQ6. As a result, the 5-bit interrupt vec-
tor is 10110.
9.4.4
The IENAM0 register is a byte-wide, read/write register that
enables or disables the individual interrupts IRQ0 through
IRQ7. The register format is shown below.
7
6
5
4
IENA(7:0)
Interrupt Enable and Mask Register 0 (IENAM0)
A bit set to 1 enables the corresponding interrupt. A bit
cleared to 0 disables the corresponding interrupt. Upon re-
set, this register is initialized to FF hex.
9.4.5
The IENAM0 register is a byte-wide, read/write register that
enables or disables the individual interrupts IRQ8 through
IRQ15. The register format is shown below.
7
6
5
4
IENA(15:8)
Interrupt Enable and Mask Register 1 (IENAM1)
A bit set to 1 enables the corresponding interrupt. A bit
cleared to 0 disables the corresponding interrupt. Upon re-
set, this register is initialized to FF hex.
9.4.6
The ISTAT0 register is a byte-wide, read-only register that in-
dicates which maskable interrupt inputs to the ICU (IRQ0
through IRQ7) are currently active. The register format is
shown below.
7
6
5
4
IST7
IST6
IST5
IST4
Interrupt Status Register 0 (ISTAT0)
IST(0-7)
Interrupt Status bits. Each bit indicates the cur-
rent status of an interrupt input to the ICU, cor-
responding to interrupts IRQ0 through IRQ7. A
bit set to 1 indicates an active interrupt input,
even when the interrupt is masked out by the
IENAM0 register. A bit cleared to 0 indicates an
inactive interrupt input.
2
1
0
EXT
3
2
1
0
ENLCK
PIN
EN
3
2
1
0
INTVECT
3
2
1
0
3
2
1
0
3
2
1
0
IST3
IST2
IST1
IST0
相關PDF資料 |
PDF描述 |
|---|---|
| CR16MHS9VJEI | Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS5 | Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS544VC | Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS544VI | Family of CompactRISC 16-Bit Microcontrollers |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CR16MHS9VJEI | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS5 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS544V8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16MNS544V9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16MNS544VC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
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