參數(shù)資料
型號(hào)： CR16MHS9VJEE
廠商： National Semiconductor Corporation
元件分類： 16位微控制器
英文描述： Family of CompactRISC 16-Bit Microcontrollers
中文描述： 家庭CompactRISC 16位微控制器
文件頁(yè)數(shù)： 95/99頁(yè)
文件大小： 449K
代理商： CR16MHS9VJEE
95
www.national.com
21.0.2
Timing Tables
Table 23
Output Signals
Symbol Figure
Description
Reference
Min (ns) Max (ns)
Tclk
a
36
CLK clock period
CLK high time
R.E. CLK to next R.E. CLK
At 2.0V
(Both Edges)
At 0.8V
(Both Edges)
0.8V to 2.0V
2.0V to 0.8V
After R.E. CLK
50
64000
a
t
CLKh
36
17.3
t
CLKl
36
CLK low time
17.3
t
CLKr
t
CLKf
36
36
CLK rise time on R.E. CLK
CLK fall time on F.E. CLK
CMOS output valid
All signals with prop. delay from CLK
R.E.
3
3
t
COv1
35
USART Output Signals
t
TXD
45
TXDn output valid
After R.E. CLKXn
35
MICROWIRE / SPI Output Signals
t
MSKh
t
MSKl
42
MICROWIRE Clock High
MICROWIRE Clock Low
MICROWIRE Clock Period
At 2.0V (both edges)
At 0.8V (both edges)
MnIDL bit = 0: R.E. MSK to next R.E. MSKn
MnIDL bit = 1: F.E. MSK to next F.E. MSKn
Data Out Bit #7 Valid
80
80
42
t
MSKp
42
200
43
t
MSKd
42
MSK Leading Edge Delayed (master
only)
MICROWIRE Data Float
b
(slave only)
MICROWIRE Data Out Hold
0.5 t
MSK
1.5 t
MSK
t
MDOf
42
After R.E. MCSn
56
t
MDOh
42
Normal Mode: After F.E. MSK
Alternate Mode: After R.E. MSK
0.0
t
MDOnf
42
MICROWIRE Data No Float
(slave only) After F.E. MWCS
MICROWIRE Data Out Valid
0
56
t
MDOv
42
Normal Mode: After F.E. MSK
Alternate Mode: After R.E. MSK
Propagation Time
Value is the same in all clocking modes of the
MICROWIRE
After R.E. of CLK
MIDL bit = 0: After F.E. MSK
MIDL bit = 1: After R.E. MSK
56
t
MITOp
46
MDODI to MDIDO
(slave only)
56
t
MRDYa
42
MRDY Active (slave only)
MRDY Inactive (slave only)
0
28
t
MRDYia
42
0
56
a. Tclk is the actual clock period of the CPU clock used in the system.
The value of Tclk is system dependent.
The maximum cycle time of 64000ns is for Power Save mode; in active mode, the maximum cycle time is limited to 250ns by the
high frequency oscillator.
b. Guaranteed by design, but not fully tested.
c. Hold time is 0 ns (min) for all outputs, unless specified otherwise.
Table 24
Input Signal Requirements
Symbol Figure
Description
Reference
Min (ns)
Max (ns)
t
XSp
t
XSh
t
XSl
t
X2p
t
X2h
36
36
36
36
36
X1 period
X1 high time, external clock
X1 low time, external clock
X2 period
a
X2 high time, external clock
R.E. X1 to next R.E. X1
At 2V level (Both Edges)
At 0.8V level (Both Edges)
R.E. X2 to next R.E. X2
At 2V level (both edges)
50
250
0.5 Tclk - 4
0.5 Tclk - 4
10,000
0.5 Tclk - 500
相關(guān)PDF資料
PDF描述
CR16MHS9VJEI Family of CompactRISC 16-Bit Microcontrollers
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參數(shù)描述
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