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| 型號： | CR16MHS9VJEE |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 16位微控制器 |
| 英文描述： | Family of CompactRISC 16-Bit Microcontrollers |
| 中文描述： | 家庭CompactRISC 16位微控制器 |
| 文件頁數(shù)： | 73/99頁 |
| 文件大?。?/td> | 449K |
| 代理商： | CR16MHS9VJEE |
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cyclic FIFO buffer, with BUFPTR pointing to the
last entry written by the A/D Converter.
18.2.2
The ADCCNT1 register is a byte-wide, read/write register
used to enable the A/D Converter and its interrupts, and also
to control the reference voltage source. When writing to this
register, all reserved bits must be written with 0 for the A/D
Converter to function properly. Changing any bits other than
ADCEN (bit 0) is not allowed while the A/D Converter is ac-
tive (ADCST.BUSY or ADCCNT2.START set). Upon reset,
all non-reserved bits are cleared to 0. The register format is
shown below.
7
6
5
4
3
2
Reserved
INTE
ADC Control 1 Register (ADCCNT1)
ADCEN
A/D Converter Enable. Setting this bit enables
the A/D Converter and allows a conversion to
be
started
by
setting
(ADCCNT2.START). Clearing the ADCEN bit
disables the A/D Converter, terminates any
conversion in progress, and clears the ADC
status flags (ADCST.EOC, ADCST.BUSY,
ADCST.OVF, and ADCCNT2.START).
Interrupt Enable. This bit enables (1) or dis-
ables (0) A/D Converter interrupts. If enabled,
and interrupt occurs at the end of a conversion
sequence or when the ADC data buffer is full,
depending on the operating mode.
All reserved bits must be written with 0 for ADC to operate
properly.
the
start
bit
INTE
18.2.3
The ADCCNT2 register is a byte-wide, read/write register
used to specify the A/D Converter operating mode and to
start conversion operations. All register fields other than the
START bit should be changed only while the A/D Converter
is inactive (START=0). Data written to the SCAN and CONT
fields is ignored if the START bit is already set. Upon reset,
the non-reserved bits of this register are cleared to 0. The
register format is shown below.
7
6
5
START
SCAN
ADC Control 2 Register (ADCCNT2)
CHANNEL
Channel Select. This 4-bit field selects one of
the eight analog input channels as follows:
0000 = ACH0
0001 = ACH1
0010 = ACH2
0011 = ACH3
0100 = ACH4
0101 = ACH5
0110 = ACH6
0111 = ACH7
1XXX = reserved
Continuous Conversion. When cleared to 0,
the A/D Converter stops operating upon com-
pletion of the programmed conversion cycle (a
single conversion or a sequence of four con-
versions on four channels). When set to 1, the
CONT
A/D Converter operates continuously by re-
peating the programmed conversion cycle.
Scan Mode. This 2-bit field selects the single-
conversion mode or 4-channel scan mode as
follows:
00 = single-conversion mode
01 = 4-channel scan mode
1X = reserved
Start Conversion. The software sets this bit to
1 to start a conversion or a 4-channel conver-
sion cycle. In the “continuous” mode, this bit re-
mains set until cleared by the software. In the
“single” (non-continuous) mode, the hardware
clears this bit upon completion of the pro-
grammed conversion cycle. The software
should not attempt to set this bit while the A/D
Converter is busy (ADCST.BUSY=1).
SCAN
START
18.2.4
The ADCCNT3 register is a byte-wide, read/write register
used to specify the analog sampling time delay and the di-
vide-by factor for generating the ADC clock. This register
should be written only when the A/D Converter is disabled
(ADCCNT1.ADCEN=0). Upon reset, the non-reserved bits of
the ADCCNT3 register are cleared to 0. The register format
is shown below.
7
6
5
Reserved
DELAY
ADC Control 3 Register (ADCCNT3)
CDIV
Clock Divide. This 3-bit field sets the divide-by
factor for generating the A/D Converter clock
from the system clock. The frequency of the A/
D Converter clock is equal to the system clock
divided by the programmed factor. The result-
ing A/D Converter clock frequency must be
less than or equal to 1 MHz. The divide-by fac-
tor is defined as follows:
000 = divide by 1
001 = divide by 2
010 = divide by 4
011 = divide by 8
100 = divide by 16
101 = divide by 32
110 = reserved
111 = reserved
Sampling Time Delay. This 3-bit field defines
the number of A/D Converter clock cycles of
delay from the time that the input channel is se-
lected until the analog voltage is sampled. The
programmed delay should be sufficient, depen-
dent on the source impedance, to allow the
sampled signal to reach its final level before the
conversion begins. The delay is defined as fol-
lows:
DELAY
000 = 1 A/D Converter clock cycle
001 = 2 A/D Converter clock cycles
010 = 4 A/D Converter clock cycles
011 = 8 A/D Converter clock cycles
100 = 16 A/D Converter clock cycles
101 = 32 A/D Converter clock cycles
1
0
Reserved
ADCEN
4
3
2
1
0
CONT
CHANNEL
4
3
2
1
0
CDIV
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PDF描述 |
|---|---|
| CR16MHS9VJEI | Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS5 | Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS544VC | Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS544VI | Family of CompactRISC 16-Bit Microcontrollers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CR16MHS9VJEI | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS5 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS544V8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16MNS544V9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16MNS544VC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
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