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15.5
The software interacts with the MICROWIRE interface by ac-
cessing the MICROWIRE registers. There are five such reg-
isters:
MICROWIRE Data Register (MWDAT)
MICROWIRE Control 1 Register (MWCTL1)
MICROWIRE Control 2 Register (MWCTL2)
MICROWIRE Control 3 Register (MWCTL3)
MICROWIRE Status Register (MWSTAT)
MICROWIRE INTERFACE REGISTERS
15.5.1
The MWDAT register is a byte-wide, read/write register used
to transmit and receive data through the MDODI and MDIDO
pins. Figure25 shows the hardware structure of the register.
MICROWIRE Data Register (MWDAT)
Reading the MWDAT register returns the data received
through the MDIDO pin in master mode or the MDODI pin in
slave mode. This data is read from a buffer. After the CPU
reads the buffer, if new data is ready in the shifter, the hard-
ware immediately transfers the new value from the shifter to
the buffer.
Writing the MWDAT register loads the shifter directly without
buffering, thus overwriting any existing data in the shifter. The
data byte is shifted out through the MDODI pin in master
mode or through the MDIDO pin in slave mode, most signifi-
cant bit first.
The MWDAT register should be accessed only after a MI-
CROWIRE interrupt. Before the CPU reads the register, the
Read Buffer Full status bit should be set (MW-
STAT.MRBF=1). Before the CPU writes the register, the MI-
CROWIRE
Busy
status
(MWSTAT.MBSY=0).
bit
should
be
cleared
For normal operation, the CPU should first read the received
data, thus allowing pending received data to be transferred
from the shifter into the MWDAT register, before it writes the
next transmit data into the MWDAT address, which loads the
shifter directly. (MWSTAT.MBSY=0 is an indicator that the
shifter is empty and ready to receive the next transmit data.)
Otherwise, a second received data byte pending in the shifter
may get overwritten by the transmit byte.
The MWDAT register contains unknown data following a re-
set operation.
15.5.2
The MWCTL1 register is a byte-wide, read/write register that
controls the operating mode of the MICROWIRE interface
module. Upon reset, all non-reserved bits are cleared to 0.
The register format is shown below.
7
6
5
4
3
2
Reserved
MEN
MIDL
MICROWIRE Control 1 Register (MWCTL1)
MMNS
MICROWIRE Master/Slave Select. When
cleared to 0, the device operates as a slave.
When set to 1, the device operates as the mas-
ter.
MICROWIRE Clocking Mode. When cleared to
0, the device uses the normal clocking mode.
When set to 1, the device uses the alternate
clocking mode. In the normal mode, the output
data is clocked out on the falling edge of MSK
and the input data is sampled on the rising
edge of MSK. In the alternate mode, the output
data is clocked out on the rising edge of MSK
and the input data is sampled on the falling
edge of MSK.
MICROWIRE Idle. This bit sets the value of the
MSK output when the MICROWIRE interface is
idle: 0 for low or 1 for high. This bit should be
changed only when the MICROWIRE interface
module is disabled (MEN=0) or when no bus
transaction is in progress (MWSTAT.MBSY=0).
MICROWIRE Enable. This bit enables (1) or
disables (0) the MICROWIRE interface mod-
ule. Clearing this bit disables the module,
clears the status bits in the MICROWIRE status
register (the MBSY, MRBF, and MOVR flags in
MWSTAT), and places the MICROWIRE inter-
face pins in the states described in Table17.
Pin Values with MICROWIRE Disabled
MSKM
MIDL
MEN
Figure 24.
MWSPI Interrupts
Figure 25.
MWDAT Register Structure
Interrupt
MWSPI
MOVR = 1
MRBF = 1
MBSY = 0
MEIW
MEIR
MEIO
SHIFTER
READ BUFFER
Write
Read
8
Data In
Data Out
1
0
MSKM
MMNS
Table 17
MSK
Master: MnIDL Bit
Slave: input
Input
Master: input
Slave: TRI-STATE
Master: known Value
Slave: input
TRI-STATE
MCS
MDIDO
MDODI
MRDY