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| 型號： | CR16MHS9VJEE |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 16位微控制器 |
| 英文描述： | Family of CompactRISC 16-Bit Microcontrollers |
| 中文描述： | 家庭CompactRISC 16位微控制器 |
| 文件頁數(shù)： | 74/99頁 |
| 文件大小： | 449K |
| 代理商： | CR16MHS9VJEE |
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74
110 = 64 A/D Converter clock cycles
111 = reserved
18.2.5
The four ADC Data Registers (ADDATA0 through ADDATA3)
are byte-wide, read/write registers that hold the conversion
results, which are stored sequentially starting with ADDATA0
and ending with ADDATA3. The results held in these regis-
ters are valid only after the ADCST.EOC flag is set. Upon re-
set, the contents of these registers are undefined.
The value read from a data register is a linear mapping of the
analog input voltage to an 8-bit value. The value 00 hex rep-
resents 0.0 volts and the value FF hex represents the refer-
ence voltage, VREF.
18.3
A/D CONVERTER PROGRAMMING
ADC Data Registers (ADDATA0-ADDATA3)
The software should set the A/D Converter configuration be-
fore it enables the A/D Converter module. The configuration
consists of the following settings:
ADC clock rate: ADCCNT3.CDIV
Sampling delay: ADCCNT3.DELAY
Interrupt enable (if required): ADCCNT1.INTE
The ADC clock is created by scaling down the system clock.
The fastest allowable clock for the A/D Converter is 1 MHz.
Therefore, for the fastest possible operation of the A/D Con-
verter, use the smallest available divide-by factor that results
in a clock frequency of 1 MHz or lower. The available divide-
by factors are 1, 2, 4, 8, 16, and 32.
For example, if the system clock is 10 MHz, use a divide-by
factor of 16. In that case, the A/D Converter clock frequency
is 625 kHz, the clock period is 1.6 microseconds, and the A/
D conversion time is 16 microseconds (ten clock A/D Con-
verter clock cycles).
The programmable sampling time delay should be made
small for faster operation, but large enough to allow the input
voltage to settle. The internal resistance and capacitance of
the A/D Converter, together with the source resistance of the
device that drives the A/D input determine the charge-up time
required for the voltage to settle. Figure35 shows a schemat-
ic of the charge-up circuit. For the values of RAIN and CAIN,
see Section21.0.
Interrupts or polling can be used to read the A/D Converter
results. For interrupts, the A/D Converter interrupt must be
enabled by setting the ADCCNT1.INTE bit. The interrupt is
cleared automatically when any one of the data registers
(ADDATA0-ADDATA3) is read. For polling, the software
reads the ADCST.EOC bit to determine whether the conver-
sion sequence is completed.
Once the A/D Converter configuration has been set up, the
software can use the following procedure to perform an A/D
conversion sequence:
1. Enable the A/D Converter by setting the ADCCNT1.AD-
CEN bit and wait 100
μ
s before performing any conver-
sion.
2. Select the operating mode and channel by writing to the
SCAN, CONT, and CHANNEL fields of the ADCCNT2
register. At the same time, start the conversion by setting
the START bit in the same register.
3. Wait until the conversion is finished, either by polling or
using the A/D Converter interrupt.
4. Read the conversion results from the data registers,
ADDATA0 through ADDATA3 (or just ADDATA0 in the
single-channel, single-conversion mode).
5. In the continuous conversion modes, repeat Step 3 and
Step 4 for as long as samples are needed. Then stop the
A/D Converter by clearing either the START bit
(ADCCNT2.START) or the A/D Converter enable bit
(ADCCNT1.ADCEN).
To minimize power consumption, the A/D Converter should
be disabled when it is not needed, especially before entering
a Power Save mode.
Figure 35.
Sample-and-Hold Charge-Up Schematic
A/D Converter
Analog
Multiplexer
Sample &
Hold
R
AIN
C
AIN
Input
signal
R
SOURCE
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| CR16MNS544VC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
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