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參數(shù)資料
| 型號： | CR16MHS9VJEE |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 16位微控制器 |
| 英文描述： | Family of CompactRISC 16-Bit Microcontrollers |
| 中文描述： | 家庭CompactRISC 16位微控制器 |
| 文件頁數(shù)： | 17/99頁 |
| 文件大?。?/td> | 449K |
| 代理商： | CR16MHS9VJEE |
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I bit
The Global Maskable Interrupt Enable (I) bit is
used to enable or disable maskable interrupts.
If this bit and the Local Maskable Interrupt En-
able (E) bit are both set to 1, all maskable inter-
rupts are accepted. Otherwise, only the non-
maskable interrupts are accepted. This bit is
automatically cleared to 0 when an interrupt oc-
curs and automatically set to 1 upon comple-
tion of an interrupt service routine.
Upon reset, all non-reserved bits of the register are cleared
to 0 except for the E bit (bit 9), which is set to 1. When a de-
vice reset occurs, the PSR contents prior to the reset are
stored into register R1, allowing the initialization software to
determine the state of the device prior to the reset operation.
6.4
The Configuration (CFG) register is a 16-bit core register that
determines the size of the INTBASE register. For the device,
the CFG register should always be left in its default state
(cleared to zero), resulting in a 16-bit INTBASE register.
CONFIGURATION REGISTER
6.5
Each instruction operates on one or more operands. An op-
erand can be a register or a memory location.
Most instructions use one, two, or three device registers as
operands. The instruction opcode specifies the registers to
be operated on. Some instructions may use an immediate
value (a value provided in the instruction itself) instead of a
register.
Memory locations are accessed only by the Load and Store
commands. The memory location to use for a particular in-
struction can be specified as an absolute, relative, or far-rel-
ative address.
The instruction set supports the following addressing modes:
Register Mode
The operand is a general-purpose regis-
ter: R0 through R13, RA, or SP. For exam-
ple:
ADDB R1, R2
Immediate
Mode
in the instruction. In a branch instruction,
the immediate operand is a displacement
from the program counter (PC). In the as-
sembly language syntax, a dollar sign indi-
cates an immediate value. For example:
MULW $4, R4
Relative Mode
The operand is located in memory. Its ad-
dress is obtained by adding the contents of
a general purpose register to the constant
value encoded into the displacement field
of the instruction. For example:
LOADW 12(R5), R6
ADDRESSING MODES
For additional information on the instruction set and instruc-
tion encoding, see the CompactRISC CR16B Programmer's
Reference manual.
6.6
STACKS
A stack is a one-dimensional data buffer in which values are
entered and removed one at a time. The last value entered is
the first one removed. A register called the stack pointer con-
tains the current address of the last item entered on the
stack. In the device, when an item is entered or “pushed”
onto the stack, the stack expands downward in memory (the
stack pointer is decremented). When an item is removed or
“popped” from the stack, the stack shrinks upward in memory
(the stack pointer is incremented).
The device uses two type of stacks: the program stack and
the interrupt stack.
The program stack is used by the software to save and re-
store register values upon entry into and exit from a subrou-
tine. The software can also use the program stack to store
local and temporary variables. The stack pointer for this
stack is the SP register.
The interrupt stack is used to save and restore the program
state when an exception occurs (an interrupt or software
trap). The on-chip hardware automatically pushes the pro-
gram state information onto the stack before the exception
service procedure is executed. Upon exit from the exception
service procedure, the hardware pops this information from
the stack and restores the program state. The stack pointer
for this stack is the ISP, or Interrupt Stack Pointer.
6.7
Table7 is a summary list of all instructions in the device in-
struction set. For each instruction, the table shows the mne-
monic with a brief description of the operation performed.
In the Mnemonic column, the lower-case letter “i” is used to
indicate the type of integer that the instruction operates on,
either “B” for byte or “W” for word. For example, the notation
ADDi for the “add” instruction means that there are two forms
of this instruction, ADDB and ADDW, which operate on bytes
and words, respectively.
Similarly, the lower-case string “cond” is used to indicate the
type of condition tested by the instruction. For example, the
notation Jcond represents a class of conditional jump instruc-
INSTRUCTION SET
A constant operand value is specified with-
Far-Relative
Mode
The operand is located in memory. Its ad-
dress is obtained by concatenating a pair
of adjacent general-purpose registers to
form a 21-bit value, and adding this value
to the constant value encoded into the dis-
placement field of the instruction. The de-
vice implementation only uses the first 64K
of the address space, so the relative mode
is sufficient to access the entire usable ad-
dress space; the far-relative mode is not
used.
Absolute Mode
The operand is located in memory. Its ad-
dress is specified within the instruction.
For example:
LOADB 4000, R6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CR16MHS9VJEI | Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS5 | Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS544VC | Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS544VI | Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS9 | Family of CompactRISC 16-Bit Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CR16MHS9VJEI | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS5 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS544V8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16MNS544V9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16MNS544VC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
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