參數(shù)資料
型號(hào)： CR16MHS9VJEE
廠商： National Semiconductor Corporation
元件分類(lèi)： 16位微控制器
英文描述： Family of CompactRISC 16-Bit Microcontrollers
中文描述： 家庭CompactRISC 16位微控制器
文件頁(yè)數(shù)： 26/99頁(yè)
文件大小： 449K
代理商： CR16MHS9VJEE
www.national.com
26
flash EEPROM data memory or access the flash EEPROM
data memory while programming the ISP memory. The 1.5
kbytes of ISP memory resides in the address range of DA00-
DFF7 and is used for storing a boot ROM. The ROM contains
the code that performs in-system programming, and is pro-
grammed at the factory. In ISP mode, code execution starts
at address DA00.
The ISP program memory and flash EEPROM data memory
share the same memory array, which makes it impossible to
access one type of memory while the other is being pro-
grammed.
The ISP memory has the following features:
— 1.5 kbytes ISP flash EEPROM program memory
— Page size of 4 words, divided into two rows of 2 words
each
— Odd and even bytes within a page can be erased sep-
arately
— The lowest 384 rows are the ISP memory, the others
are data memory; A1 selects the columns and A[11:2]
select the rows
— 30
μ
s programming pulse width per word
— Page mode erase with 1ms pulse
— All erased memory bits read 1
— Fast read access time
— Requires valid key for program and erase to proceed
— Provide memory protection and security features for
flash EEPROM program memory
— Security features may limit accesses to ISP memory
— Disable memory when address is out of range to pre-
vent accessing data memory
— Provide busy status during programming and erase
— Read/write accesses disabled during programming/
erase
— Programming high voltage and timing generated on-
chip
— Support flash memory test mode with PADX for securi-
ty overrides
8.4.1
The ISP flash EEPROM program memory read accesses can
operate without wait cycles with a CPU clock rate of up to
20MHz in the normal mode. At higher clock rates, read ac-
cesses can operate with one wait state.
The programmed number of wait cycles used (either zero or
one) is controlled by BIU Configuration (BCFG) register and
the Static Zone 0 Configuration (SZOFG0) register. These
registers are described in Section7.2.1 and 7.2.3.
Reading
8.4.2
All program and erase operations must be preceded by writ-
ing the proper key to the program memory key register ISP-
KEY. The programming code can reside in the in-system
RAM, but cannot reside in the ISP flash EEPROM program
memory or flash EEPROM data memory as accesses within
these ranges are not permitted while ISP flash EEPROM pro-
gram memory is being programmed.
The ISP flash memory is divided into 192 pages, each page
containing 4 words (each 16 bits wide). Each page is further
divided into two rows. Erase is carried out one page at a time,
whereas programming is carried out one row (or one partial
row) at a time.
User-Coded Programming Routines
Once an erase or programming operation is started, the PG-
MBUSY bit in the MSTAT register is automatically set, and
then cleared when the operation is complete. All high-voltage
pulses and timing needed for programming and erasing are
provided internally. The program memory cannot be access-
ed while the PGMBUSY bit is set.
Erase Procedure
Erasing a page requires the following code sequence:
1. Verify that the MSTAT.PGMBUSY bit is cleared.
2. Set the DMCSR.ERASE bit to 1.
3. Locally disable interrupts.
4. Write proper key value to the ISPKEY register.
5. Write to any valid page to be erased.
6. Re-enable interrupts disabled in Step 3.
7. Set the DMCSR.ERASE bit to 0.
8.4.3
Programming is done by writing one byte or word at a time
and should be done on already erased memory.
Programming the ISP flash EEPROM program memory re-
quires the following code sequence:
1. Verify that the MSTAT.PGMBUSY bit is cleared.
2. Locally disable interrupts.
3. Write proper key value to the ISPKEY register.
4. Write a byte or word to the addressed location.
5. Re-enable interrupts disabled in Step 2.
Programmed values can be verified through normal read op-
erations.
If a reset occurs in the middle of an erase or programming
operation, the operation is terminated. The rest is extended
until the flash EEPROM memory returns to the idle state.
Programming Procedure
8.4.4
The program and erase timing are controlled by the flash EE-
PROM data memory logic.
Erase and Programming Timing
8.4.5
The last byte of the ISP memory are reserved for special
functions and provide memory protection and security for the
flash EEPROM program memory. Read and write protection
is provided.
Protection Features
8.4.6
The program memory has security features to prevent unau-
thorized access to the program code and unintentional pro-
gramming. These features are invoked by programming a
non-volatile control register, the Flash EEPROM Security
(FLSEC) register. This register contains a read-access con-
trol bit and a write-access control bit.
Both control bits are initially set to 1. Programming the read-
access bit to 0 prevents outside access to the program code;
any attempt to access the code from outside returns all ze-
ros. Programming the write-access bit to 0 prevents any fur-
ther programming of the flash program memory, thus
protecting the program code from overwriting.
Programming either bit to 0 (or both bits to 0) also prevents
any further changes to the FLSEC register itself. Thus, invok-
ing read protection and/or write protection is permanent.
Program Memory Security Features
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