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參數(shù)資料
| 型號(hào)： | CR16MHS9VJEE |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 16位微控制器 |
| 英文描述： | Family of CompactRISC 16-Bit Microcontrollers |
| 中文描述： | 家庭CompactRISC 16位微控制器 |
| 文件頁數(shù)： | 22/99頁 |
| 文件大?。?/td> | 449K |
| 代理商： | CR16MHS9VJEE |
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22
8.0
The CompactRISC architecture supports a uniform linear ad-
dress space of 2 megabytes, addressed by 21 bits. The de-
vice implementation of this architecture uses only the lowest
64 kbytes of address space, addressed by 16 bits. Each
memory location contains a byte consisting of eight bits.
Four types of on-chip memory occupy specific intervals with-
in the address space: 48 kbytes of flash program memory,
1.5 kbytes of ISP memory, 2 kbytes of static RAM, and 640
bytes of EEPROM data memory. All of these memories are
16 bits wide, but their contents can be accessed either as
bytes (eight bits wide) or words (16 bits wide).
The CPU core uses the Load and Store instructions to ac-
cess memory. These instructions can operate on bytes or
words. For a byte access, the CPU operates on a single byte
occupying a specified memory address. For a word access,
the CPU operates on two consecutive bytes. In that case, the
specified address refers to the least significant byte of the
data value; the most significant byte is located at the next
higher address. Thus, the ordering of bytes in memory is
from least to most significant byte. For more efficient data ac-
cess operations, 16-bit variables should be stored starting at
word boundaries (at even address).
Memory
8.1
The flash program memory is used to store the application
program. The 48 kbytes of this memory reside in the address
range of 0000-BFFF hex. A normal CPU write operation to
this memory has no effect.
The program memory has the following features:
48 kbytes arranged as 24K by 16 bits
Page size of 64 words, divided into two rows of 32 words
30
μ
s programming pulse per word
Page mode erase with a 1 ms pulse
Programming high voltage and timing generated on-chip
Boot-ROM controlled in-system programming capability
User-coded programming capability
Security features to limit read/write access
FLASH PROGRAM MEMORY
8.1.1
Program memory read accesses can operate without wait cy-
cles with a CPU clock rate of up to 12.5 MHz in the normal
mode. At higher clock rates, memory read accesses can op-
erate with one wait state.
The programmed number of wait cycles used (either zero or
one) is controlled by the BIU Configuration (BCFG) register
and the Static Zone 0 Configuration (SZCFG0) register.
These registers are described in Section7.2.1 and 7.2.3.
Reading
8.1.2
The flash program memory can be programmed either with
device plugged into an EPROM programmer unit (external
programming) or with the device installed in the application
system (in-system programming). The device internally gen-
erates the necessary voltages for programming. No addition-
al power supply is required.
Programming the memory requires placing the device in a
special programming mode. Programming commands is-
sued while the device is in its normal operating mode are ig-
nored.
Conventional Programming Modes
To enter one of the programming modes, the device must be
reset with the ENV1 and ENV0 pins configured to select the
desired mode: Test Mode for external programming or In-
System Programming mode for in-system programming.
Once the device enters the programming mode, the pro-
gramming software performs the task of downloading the
program code through a serial port and writing the code to
the EEPROM memory. The software used for programming
the EEPROM resides outside of the device for external pro-
gramming or in the on-chip boot ROM for conventional in-
system programming.
8.1.3
Instead of using an EPROM programmer unit or the conven-
tional in-system programming mode, you can write your own
processor code to program and erase the flash program
memory. Writing your own code is more flexible than using
the other programming methods. Like the conventional in-
system programming mode, you can program the device
while it is installed in the system, but no PC is required to
download the program data. It is not necessary to reset the
device or use the ENV0/ENV1 pins to configure the device.
If you write your own flash EEPROM programming code, the
code must reside in the 2 kbytes of RAM memory, in the ad-
dress range of E000-E7FF. This is because the entire flash
program memory becomes unavailable when you program or
erase any part of that memory.
Also, for programming the flash program memory, you need
to design a protocol for the device to obtain the programming
data. For example, you can use the on-chip USART to obtain
the programming data from an external device through a se-
rial interface.
The flash program memory is divided into 384 pages, each
page containing 64 words (each 16 bits wide). Each page is
further divided into two rows of 32 words. Erasure is carried
out one page at a time, whereas programming is carried out
one row (or one partial row) at a time.
Once an erase or programming operation is started, the
PGMBUSY bit in the MSTAT register is automatically set, and
then cleared when the operation is complete. All high-voltage
pulses and timing needed for programming and erasing are
provided internally. The program memory cannot be access-
ed while the PGMBUSY bit is set.
User-Coded Programming Routines
8.1.4
The flash EEPROM program memory programming and
erase can be performed using different methods. It can be
done through user code that is stored in system RAM, or
through In-System-Programming mode, but should not be
programmed through the flash EEPROM program memory it-
self as no instruction or data can be fetched from it while it is
being programmed. All program and erase operations must
be preceded immediately by writing the proper key to the pro-
gram memory key register PGMKEY.
The flash EEPROM program memory is divided into 384 pag-
es, each page containing 64 words (each 16 bits wide). Each
page is further divided into two adjacent rows.
A page erase
will erase one page. Programming is done by writing to all
the words within a row, one word following another sequen-
Flash EEPROM Programming and Verify
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CR16MHS9VJEI | Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS5 | Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS544VC | Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS544VI | Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS9 | Family of CompactRISC 16-Bit Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CR16MHS9VJEI | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS5 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
| CR16MNS544V8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16MNS544V9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16MNS544VC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
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