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The register format is shown below.
12.3
WAKE-UP SOURCE SELECT REGISTER
(WKCTRL)
The Wake-Up Source Select (WKCTRL) register is a byte-
wide read/write register that selects the trigger source for the
first of the eight channels. Register bit 0 controls this func-
tion; the seven higher-order bits are reserved. The register
format is shown below.
7
6
5
4
3
2
Reserved
WKSEL0
Wake-Up Select 0. This bit cleared to 0 selects
the WUI0 pin as the trigger source. This bit set
to 1 selects the T0OUT signal from the Timing
and Watchdog (TWM) module as the trigger
source, which can be used to wake up the de-
vice after a programmed time interval. This bit
is cleared upon reset. All reserved bits must be
written with 0 for this module to function prop-
erly.
12.4
WAKE-UP PENDING REGISTER (WKPND)
The Wake-Up Pending (WKPND) register is a byte-wide
read/write register in which the Multi-Input Wake-Up module
latches any detected trigger conditions. Register bits 0
through 7 serve as latches for channels WUI0 through WUI7,
respectively. A bit cleared to 0 indicates that no trigger con-
dition has occurred. A bit set to 1 indicates that a trigger con-
dition has occurred and is pending on the corresponding
channel. This register is cleared upon reset.
The CPU can only write a 1 to any bit position in this register.
If the CPU attempts to write a 0, it has no effect on that bit.
To clear a bit in this register, the CPU must use the WKPCL
register (described below). This implementation prevents a
potential hardware-software conflict during a read-modify-
write operation on the WKPND register.
The register format is shown below.
12.5
WAKE-UP PENDING CLEAR REGISTER
(WKPCL)
The Wake-Up Pending Clear (WKPCL) register is a byte-
wide write-only register that lets the CPU clear bits in the WK-
PND register. Writing a 1 to a bit position in the WKPCL reg-
ister clears the corresponding bit in the WKPND register.
Writing a 0 leaves the corresponding bit in the WKPND reg-
ister unchanged.
Reading this register location returns unknown data. There-
fore, do not use a read-modify-write sequence to set the in-
dividual bits. In other words, do not attempt to read the
register and do a logical OR with the register value. Instead,
just write the mask directly to the register address.
The register format is shown below.
12.6
PROGRAMMING PROCEDURES
To set up and use the Multi-Input Wake-Up function, use the
following procedure. Performing the steps in the order shown
will prevent false triggering of a wake-up condition. This
same procedure should be used following a reset because
the wake-up inputs are left floating, resulting in unknown data
on the input pins.
1. Clear the WKENA register to disable the wake-up chan-
nels.
2. If the input originates from an I/O port (the usual case),
set the corresponding bit in the port direction register to
configure the I/O pin to operate as an input.
3. Write the WKEDG register to select the desired type of
edge sensitivity (clear to 0 for rising edge, set to 1 for fall-
ing edge).
4. Set all bits in the WKPCL register to clear any pending
bits in the WKPND register.
5. Set the bits in the WKENA register corresponding to the
wake-up channels to be activated.
To change the edge sensitivity of a wake-up channel, use the
following procedure. Performing the steps in the order shown
will prevent false triggering of a wake-up/interrupt condition.
1. Clear the WKENA bit associated with the input to be re-
programmed.
2. Write the new value to the corresponding bit position in
the WKEDG register to reprogram the edge sensitivity of
the input.
3. Set the corresponding bit in the WKPCL register to clear
the pending bit in the WKPND register.
4. Set the same WKENA bit to re-enable the wake-up func-
tion.
7
6
5
4
3
2
1
0
WKEN7 WKEN6 WKEN5 WKEN4 WKEN3 WKEN2 WKEN1 WKEN0
1
0
WKSEL0
7
6
5
4
3
2
1
0
WKPD7 WKPD6 WKPD5 WKPD4 WKPD3 WKPD2 WKPD1 WKPD0
7
6
5
4
3
2
1
0
WKCL7
WKCL6 WKCL5
WKCL4
WKCL3
WKCL2 WKCL1
WKCL0