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| 型號： | CR16MHS9VJEE |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 16位微控制器 |
| 英文描述： | Family of CompactRISC 16-Bit Microcontrollers |
| 中文描述： | 家庭CompactRISC 16位微控制器 |
| 文件頁數(shù)： | 34/99頁 |
| 文件大小： | 449K |
| 代理商： | CR16MHS9VJEE |
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34
10.0 Power Management
The Power Management Module (PMM) improves the effi-
ciency of the device by changing the operating mode (and
therefore the power consumption) according to the current
level of device activity.
The device can operate in any of four power modes:
Active
Power Save
Idle
Halt
Table12 summarizes the main properties of the four operat-
ing modes: the state of the high-frequency oscillator (on or
off), the type of clock used by most modules, and the clock
used by the Timing and Watchdog Module (TWM).
Table 12
Power Mode Operating Summary
The low-frequency oscillator continues to operate in all four
modes and power must be provided continuously to the de-
vice power supply pins. In the Halt mode, however, the inter-
nal SLCLK does not toggle, and as a result, the TWM timer
and Watchdog Module do not operate. For the Power Save
and Idle modes, the high-frequency oscillator can be turned
on or off under software control, as long as the low-frequency
oscillator exists in the applicable device package.
10.1
ACTIVE MODE
In the Active mode, all device modules are fully operational.
This is the operating mode upon reset. Most device modules
use the clock generated by the high-frequency clock oscilla-
tor. The clock rate is determined by the external crystal net-
work.
Power consumption in the Active mode can be reduced by
selectively disabling inactive modules and/or by executing
the WAIT instruction. When WAIT is executed, the core stops
executing new instructions and waits for an interrupt.
10.2
In the Power Save mode, all device modules operate off the
low-frequency clock. If the low-frequency clock is generated
from an external crystal network, the high-frequency clock
oscillator can be turned off to further reduce power consump-
tion.
All on-chip modules continue to operate in the Power Save
mode, with the SLCLK acting as their system clock. If this
mode is entered by using the WAIT command, the CPU is in-
active and waits for an interrupt to wake up. Otherwise, CPU
continues to function normally at the lower frequency of the
slow clock.
The low frequency of the clock in Power Save mode limits the
operation of modules such as the USARTs, MICROWIRE in-
POWER SAVE MODE
terface, A/D Converter, and timers because they are driven
by the slow clock rather than the normal high-speed clock. In
order to work properly in Power Save mode, modules that
perform real-time operations (such as a USART baud rate
generator) must be reprogrammed to use the slower clock.
To reduce power consumption as much as possible, the pro-
gram should execute a WAIT instruction during periods of
CPU inactivity.
10.3
In the Idle mode, the clock is stopped for most of the device.
Only the Power Management Module and Timing and Watch-
dog Module continue to operate. Both of these modules use
the slow clock in this mode.
IDLE MODE
10.4
In the Halt mode, all device clocks are disabled and the high-
frequency oscillator is shut off. In this mode, the device con-
sumes the least possible power while maintaining the device
memory and register contents. The low-frequency oscillator
continues to operate in this mode, but with very low power
consumption due to its power-optimized design.
HALT MODE
10.5
SWITCHING BETWEEN POWER MODES
Switching from a higher to a lower power consumption mode
is accomplished by writing an appropriate value to the Power
Management Control/Status Register (PMCSR). Switching
from a lower power consumption mode to the Active mode is
usually triggered by a hardware interrupt. Figure5 shows the
four power consumption modes and the events that trigger a
transition from one mode to another.
Some of the power-up transitions are based on the occur-
rence of a wake-up event. An event of this type can be either
a maskable interrupt or a non-maskable interrupt (NMI). All of
the maskable hardware wake-up events are gathered and
processed by the Multi-Input Wake-Up Module, which is ac-
tive in all modes. Once a wake-up event is detected, it is
latched until an interrupt acknowledge cycle occurs or a reset
is applied.
A wake-up event causes a transition to the Active mode and
restores normal clock operation, but does not start execution
Mode
High-Frequency
Oscillator
Clock Used TWM Clock
Active
Power Save On or Off
Idle
Halt
On
Main Clock
Slow Clock
None
None
Slow Clock
Slow Clock
Slow Clock
None
On or Off
Off
Figure 5.
Power Modes and Transitions
Active
Power Save
IDLE =1
and WAIT
Idle
Halt
PSM =1
HW event
or PSM =0
HALT =1
and WAIT
HW event
Reset
HW event
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| CR16MNS544VC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
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