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參數(shù)資料
| 型號： | CR16MHS9VJEE |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 16位微控制器 |
| 英文描述： | Family of CompactRISC 16-Bit Microcontrollers |
| 中文描述： | 家庭CompactRISC 16位微控制器 |
| 文件頁數(shù)： | 25/99頁 |
| 文件大?。?/td> | 449K |
| 代理商： | CR16MHS9VJEE |
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8.2
RAM MEMORY
The static RAM memory is used for temporary storage of
data and for the program and interrupt stacks. The 2 kbytes
of this memory reside in the address range of E000-E7FF
hex. Each memory access requires one clock cycle, for a
byte or word access. For non-aligned word access, each
memory access requires multiple clock cycles. No wait cy-
cles or hold cycles are required.
8.3
EEPROM DATA MEMORY
The EEPROM data memory is used for non-volatile storage
of data. The 640 bytes of this memory reside in the address
range of F000-F27F hex. The CPU reads or writes this mem-
ory by using ordinary byte-wide or word-wide memory ac-
cess commands.
8.3.1
EEPROM data memory read accesses can operate without
wait cycles with a CPU clock rate of up to 12.5 MHz in the
normal mode. At higher clock rates, read accesses can oper-
ate with one wait state.
The programmed number of wait cycles used (either zero or
one) is controlled by a bit in the Module Configuration regis-
ter (MCFG.FEEDM). This register is described in
Section4.2.
Reading
8.3.2
Before you begin programming the EEPROM data memory,
you should set the value in the EEPROM Data Memory Pres-
caler register. This register sets the prescaler used to gener-
ate the data memory programming clock from the system
clock, as described in Section8.3.4.
After the CPU performs a write to the EEPROM data memo-
ry, the on-chip hardware completes the EEPROM program-
ming in the background. When programming begins, the on-
chip hardware sets the DMCSR.DMBUSY bit to 1, and also
sets the MSTAT.PGMBUSY bit to 1. When programming is
completed, it resets these status bits back to 0. Once the
software writes to the EEPROM data memory, it should not
attempt to access the EEPROM data memory again until pro-
gramming is completed and the status bit is reset to 0.
The device hardware internally generates the voltages and
timing signals necessary for programming. No additional
power supply is required, nor any software required except to
check the status bit for completion of programming. The min-
imum time required to erase and reprogram a byte or word is
1.16 ms. The programmed values can be verified by using
normal memory read operations.
If a reset occurs during a programming or erase operation,
the operation is terminated. The reset is extended until the
flash memory returns to the idle state.
The EEPROM data memory does not have permanent read-
protection or write-protection features like those available for
the EEPROM program memory. However, the Data Memory
Write Key Register provides a way to “l(fā)ock” the data written
to the data memory.
Programming
8.3.3
Data Memory Control and Status Register
(DMCSR)
The DMCSR register is a byte-wide, read/write register used
with the EEPROM data memory. There are two status/control
bits, as shown in the register format below.
7
6
5
4
3
2
Reserved
DMBUSY
ERASE
Erase ISP Flash Program Memory Page.
When set (1) a valid write to the ISP flash EE-
PROM program memory will erase the entire
ISP flash EEPROM program memory page
pointed to by the write address rather than per-
forming a write to the addressed memory loca-
tion. This bit should be cleared to 0 and remain
cleared after the write operation.
Data Memory Busy. This bit is automatically set
to 1 when the EEPROM data memory is busy
being programmed, and cleared to 0 at all other
times. (The MSTAT.PGMBUSY is also set to 1
whenever the DMBUSY bit is set to 1.)
Upon reset, the DMCSR register is cleared to zero when the
flash memory on the chip is in the idle state.
DMBUSY
8.3.4
The DMPSLR register is a byte-wide, read/write register that
selects the prescaler divider ratio for the EEPROM data
memory programming clock. Before you write to the data
memory for the first time, you should program the DMPSLR
register with the proper prescaler value, an 8-bit value called
FTDIV. The device divides the system clock by (FTDIV+1) to
produce the data memory programming clock.
You should choose a value of FTDIV to produce a clock of the
highest possible frequency that is equal to or just less than
200 kHz. Upon reset, this register is programmed by default
with the value 33 hex (51 decimal), which is an appropriate
setting for a 10.4 MHz system clock.
Data Memory Prescaler Register (DMPSLR)
8.3.5
The DMKEY register is a byte-wide, read/write register that
provides a way to “l(fā)ock” the data contained in the EEPROM
data memory. Upon reset, the register is automatically set to
C9 hex, which is the key value. Writing to the EEPROM data
memory is allowed as long as the DMKEY register contains
this value. When the register contains any value other than
C9 hex, writing the EEPROM data memory is disallowed.
To “l(fā)ock” the current data stored in the data memory, write an-
other value (such as 00 hex) to the DMKEY register. To “un-
lock” the data memory, write the value C9 hex to the DMKEY
register.
Note:
Operation of this register is different from the
PGMKEY register used with the program memory. It is not
necessary to write the key value to DMKEY every time you
write to the data memory.
Data Memory Write Key Register (DMKEY)
8.4
The In-System Program memory is part of the flash memory
array that contains the flash EEPROM data memory. It is not
possible to access the ISP memory while programming the
ISP MEMORY
1
0
ERASE
Reserved
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| CR16MHS9VJEI | Family of CompactRISC 16-Bit Microcontrollers |
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相關(guān)代理商/技術(shù)參數(shù) |
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| CR16MHS9VJEI | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
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| CR16MNS544V9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16MNS544VC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
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