
Bt848/848A/849A
Single-Chip Video Capture for PCI
Brooktree
80
PC B
OARD
L
AYOUT
C
ONSIDERATIONS
Power Planes
L848A_A
Power Planes
The power plane area should encompass all Bt848 power pins, voltage reference
circuitry, power supply bypass circuitry for the Bt848, the analog input traces, any
input amplifiers, and all the digital signal traces leading to the Bt848.
The Bt848 has digital power (VDD) and analog power (VAA and VPOS). The
layout for the power plane should be such that the two planes are at the same elec-
trical potential, but they should be isolated from each other in the areas surround-
ing the chip. Also, the source path for current should be through the digital plane.
This is the same layout as shown for the ground plane (Figure 38). When using a
regulator, circuitry must be included to ensure proper power sequencing. The cir-
cuitry shown in Figure 39 should help in this regard.
Supply Decoupling
The bypass capacitors should be installed with the shortest leads possible, consis-
tent with reliable operation, to reduce the lead inductance. These capacitors should
also be placed as close as possible to the device.
Each group of VAA and VDD pins should have a 0.1
μ
F ceramic bypass capac-
itor to ground, located as close as possible to the device.
Additionally, 10
μ
F capacitors should be connected between the analog power
and ground planes, as well as between the digital power and ground planes. These
capacitors are at the same electrical potential, but are physically separate, and pro-
vide additional decoupling by being physically close to the Bt848 power and
ground planes. See Figure 40 for additional information about power supply de-
coupling.
Digital Signal
Interconnect
The digital signals of the Bt848 should be isolated as much as possible from the an-
alog signals and other analog circuitry. Also, the digital signals should not overlay
the analog power plane.
Any termination resistors for the digital signals should be connected to the dig-
ital PCB power and ground planes.
Analog Signal
Interconnect
Long lengths of closely-spaced parallel video signals should be avoided to mini-
mize crosstalk. Ideally, there should be a ground line between the video signal trac-
es driving the YIN and CIN inputs.
Also, high-speed TTL signals should not be routed close to the analog signals to
minimize noise coupling.