參數(shù)資料
型號： BT849A
英文描述： Single-Chip Video Capture for PCI
中文描述： 單芯片的PCI視頻捕捉
文件頁數(shù)： 18/141頁
文件大?。?/td> 1149K
代理商： BT849A
Bt848/848A/849A
Single-Chip Video Capture for PCI
Brooktree
8
F
UNCTIONAL
D
ESCRIPTION
Pin Descriptions
L848A_A
51
PAR
I/O
Parity
This three-state, bi-directional, I/O pin provides even parity
across AD[31:0] and CBE[3:0]. This means that the number
of 1’s on PAR, AD[31:0], and CBE[3:0] equals an even num-
ber.
PAR is stable and valid one clock after the address phase.
For data phases, PAR is stable and valid one clock after
either TRDY is asserted on a read or IRDY is asserted on a
write. Once valid, PAR remains valid until one clock after the
completion of the current data phase. PAR and AD[31:0] have
the same timing, but PAR is delayed by one clock. The target
drives PAR for read data phases; the master drives PAR for
address and write data phases.
42
FRAME
I/O
Cycle Frame
This sustained three-state signal is driven by the current
master to indicate the beginning and duration of an access.
FRAME is asserted to signal the beginning of a bus transac-
tion. Data transfer continues throughout assertion. At deas-
sertion, the transaction is in the final data phase.
43
IRDY
I/O
Initiator Ready
This sustained three-state signal indicates the bus master’s
readiness to complete the current data phase.
IRDY is used in conjunction with TRDY. When both IRDY
and TRDY are asserted, a data phase is completed on that
clock. During a read, IRDY indicates when the initiator is
ready to accept data. During a write, IRDY indicates when the
initiator has placed valid data on AD[31:0]. Wait cycles are
inserted until both IRDY and TRDY are asserted together.
44
TRDY
I/O
Target Ready
This sustained three-state signal indicates the target’s readi-
ness to complete the current data phase.
IRDY is used in conjunction with TRDY. When both IRDY
and TRDY are asserted, a data phase is completed on that
clock. During a read, TRDY indicates when the target is pre-
senting data. During a write, TRDY indicates when the target
is ready to accept the data. Wait cycles are inserted until both
IRDY and TRDY are asserted together.
45
DEVSEL
I/O
Device Select
This sustained three-state signal indicates device selection.
When actively driven, DEVSEL indicates the driving device
has decoded its address as the target of the current access.
46
STOP
I/O
Stop
This sustained three-state signal indicates the target is
requesting the master to stop the current transaction.
49
PERR
I/O
Parity Error
Report data parity error.
14
REQ
O
Request
Agent desires bus.
8
INTA
O
Interrupt A
This signal is an open drain interrupt output.
50
SERR
O
System Error
Report address parity error. Open drain.
See PCI Specification 2.1 for further documentation
Table 2. Pin Descriptions Grouped by Pin Function
(2 of 6)
Pin #
Pin Name
I/O
Signal
Description
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