參數(shù)資料
型號: BT849A
英文描述: Single-Chip Video Capture for PCI
中文描述: 單芯片的PCI視頻捕捉
文件頁數(shù): 127/141頁
文件大?。?/td> 1149K
代理商: BT849A
Brooktree
117
C
ONTROL
R
EGISTER
D
EFINITIONS
I
2
C Data/Control
L848A_A
Bt848/848A/849A
Single-Chip Video Capture for PCI
I
2
C Data/Control
Memory Mapped Location 0x110
The data bytes can be read back after writing if I2CDIV is set to 0 (software drive mode). Otherwise, since the register
will be in shift mode during I2C circuit mode, the read data will be different from the data written to the register. The
data read from the slave will be stable after issuing a read slave transaction and I2CDONE is set.
Bits
Type
Default
Name
Description
[31:24]
RW
I2CDB0
First byte sent in an I
2
C transaction. Typically this will be the base or
chip 7-bit address and the R/W bit.
[23:16]
RW
I2CDB1
Second byte sent in an I
2
C write transaction, usually a sub-address.
[15:8]
RW
I2CDB2
Third byte sent in an I
2
C write transaction, usually the data byte. After
a read transaction, this byte register will contain the data read from
the slave.
[7:4]
RW
00000
I2CDIV
Programmable divider after PCI clock/16 for SDA/SCL bit stream gen-
eration. This value must be set to zero for software mode.
[3]
RW
0
I2CSYNC
A value of 1 enables bit-level clock synchronization which allows the
slave to insert wait states.
[2]
RW
0
I2CW3B
A value of 0 indicates a write transaction is to consist of sending two
bytes I2CDB(0–1), while a value of 1 indicates a 3-byte write trans-
mission.
[1]
RW
1
I2CSCL
A value of 1 releases the SCL output, and a 0 forces the SCL output
low. This bit must be set to a 1 during hardware mode. This override is
for direct software control of the bus. Reading this bit provides access
to the buffered SCL input pin.
[0]
RW
1
I2CSDA
A value of 1 releases the SDA output, and a 0 forces the SDA output
low. This bit must be set to a 1 during hardware mode. This override is
for direct software control of the bus. Reading this bit provides access
to the buffered SDA input pin.
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