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參數(shù)資料
| 型號(hào)： | BT849A |
| 英文描述： | Single-Chip Video Capture for PCI |
| 中文描述： | 單芯片的PCI視頻捕捉 |
| 文件頁(yè)數(shù)： | 70/141頁(yè) |
| 文件大?。?/td> | 1149K |
| 代理商： | BT849A |
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Bt848/848A/849A
Single-Chip Video Capture for PCI
Brooktree
60
E
LECTRICAL
I
NTERFACES
Input Interface
L848A_A
Flash A/D Converters
The Bt848 uses two on-chip flash A/D converters to digitize the video signals.
YREF+, CREF+ and YREF–, CREF– are the respective top and bottom of the in-
ternal resistor ladders.
The input video is always AC-coupled to the decoder. CREF– and YREF– are
connected to analog ground. The voltage levels for YREF+ and CREF+ are
controlled by the gain control circuitry. If the input video momentarily exceeds the
corresponding REF+ voltage it is indicated by LOF and COF in the STATUS
register.
A/D Clamping
An internally generated clamp control signal is used to clamp the inputs of the A/D
converter for DC restoration of the video signals. Clamping for both the YIN and
CIN analog inputs occurs within the horizontal sync tip. The YIN input is always
restored to ground while the CIN input is always restored to CLEVEL. CLEVEL
must be set with an external resistor network so that it is biased to the midpoint be-
tween CREF– and CREF+. External clamping is not required because internal
clamping is automatically performed (the Bt848A and Bt849A do not require that
CLEVEL be connected to a resistor network).
Power-up Operation
Upon power-up, the status of the Bt848’s registers is indeterminate. The RST sig-
nal must be asserted to set the register bits to their default values. The Bt848 device
defaults to NTSC-M format upon reset.
Automatic Gain Controls
The REFOUT, CREF+ and YREF+ pins should be connected together as shown in
Figure 25. In this configuration, the Bt848 controls the voltage for the top of the
reference ladder for each A/D. The automatic gain control adjusts the YREF+ and
CREF+ voltage levels until the back porch of the Y video input generates a digital
code 0x38 from the A/D.
Crystal Inputs and Clock
Generation
The Bt848 has two pairs of pins, XT0I/XT0O and XT1I/XT1O, that are used to in-
put a clock source. If both NTSC and PAL video are being digitized, both clock in-
puts must be implemented. The XT0 port is used to decode NTSC video and must
be configured with a 28.63636 MHz source. The XT1 port is used to decode PAL
video and must be configured with a 35.46895 MHz source.
If the Bt848 is configured to decode either NTSC or PAL but not both, then only
one clock source must be provided to the chip and it must be connected to the
XT0I/XT0O port. If a crystal input is not used, the crystal amplifiers are internally
shut down to save power.
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