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參數(shù)資料
| 型號： | BT849A |
| 英文描述： | Single-Chip Video Capture for PCI |
| 中文描述： | 單芯片的PCI視頻捕捉 |
| 文件頁數(shù)： | 41/141頁 |
| 文件大?。?/td> | 1149K |
| 代理商： | BT849A |
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Brooktree
31
F
UNCTIONAL
D
ESCRIPTION
Video Scaling, Cropping, and Temporal Decimation
L848A_A
Bt848/848A/849A
Single-Chip Video Capture for PCI
The Vertical Delay Register (VDELAY)
is programmed with the delay be-
tween the rising edge of VRESET and the start of active video lines. It determines
how many lines to skip before initiating the ACTIVE signal. It is programmed with
the number of lines to skip at the beginning of a frame.
The Vertical Active Register (VACTIVE)
is programmed with the number of
lines used in the vertical scaling process. The actual number of vertical lines output
from the Bt848 is equal to this register times the vertical scaling ratio. If VSCALE
is set to 0x1A00 (4:1) then the actual number of lines output is VACTIVE/4. If VS-
CALE is set to 0x0000 (1:1) then VACTIVE contains the actual number of vertical
lines output.
Note: It is important to note the difference between the implementation of the
horizontal registers (HSCALE, HDELAY, and HACTIVE) and the vertical regis-
ters (VSCALE, VDELAY, and VACTIVE). Horizontally, HDELAY and HAC-
TIVE are programmed with respect to the scaled pixels defined by HSCALE.
Vertically, VDELAY and VACTIVE are programmed with respect to the number of
lines before scaling (before VSCALE is applied).
Temporal Decimation
Temporal decimation provides a solution for video synchronization during periods
when full frame rate can not be supported due to bandwidth and system restric-
tions.
For example, when capturing live video for storage, system limitations such as
hard disk transfer rates or system bus bandwidth may limit the frame capture rate.
If these restrictions limit the frame rate to 15 frames per second, the Bt848’s time
scaling operation will enable the system to capture every other frame instead of al-
lowing the hard disk timing restrictions to dictate which frame to capture. This
maintains an even distribution of captured frames and alleviates the “jerky” effects
caused by systems that simply burst in data when the bandwidth becomes avail-
able.
The Bt848 provides temporal decimation on either a field or frame basis. The
temporal decimation register (TDEC) is loaded with a value from 1 to 60 (NTSC)
or 1 to 50 (PAL/SECAM). This value is the number of fields or frames skipped by
the chip during a sequence of 60 for NTSC or 50 for PAL/SECAM. Skipped fields
and frames are considered inactive, which is indicated by the ACTIVE pin remain-
ing low.
Figure 16. Regions of the Video Signal
HDELAY
HACTIVE
Front
Porch
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| BT850-ST-T/R | 功能描述:BTV4.2 DUAL MODE USB HCI MODULEE 制造商:laird - wireless & thermal systems 系列:* 零件狀態(tài):在售 標準包裝:2,500 |
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