參數(shù)資料
型號： BT849A
英文描述： Single-Chip Video Capture for PCI
中文描述： 單芯片的PCI視頻捕捉
文件頁數(shù)： 54/141頁
文件大?。?/td> 1149K
代理商： BT849A
Bt848/848A/849A
Single-Chip Video Capture for PCI
Brooktree
44
F
UNCTIONAL
D
ESCRIPTION
Video and Control Data FIFO
L848A_A
FIFO Data Interface
Loading data into the FIFO can begin only when valid pixels are present during the
even or the odd field. The pixel DWORD PD[31:0] is stored in FI[31:0], and the
video control code STATUS[3:0] is stored in FI[35:32]. The VBI data will be in-
cluded in the captured sequence if VBI capture capability is enabled.
The four bits of STATUS are used to encode information about the pixel data
and the state of the video timing unit (see Table 9). Video timing and control infor-
mation are passed through the FIFO along with the data stream. The FIFO buffer
isolates the asynchronous video input and PCI output domains. Control of the in-
put stream can only occur from the video timing unit of the video decoder and from
the configured registers. The interaction and synchronization of the DMA Control-
ler and the RISC instruction sequence will rely solely on the output side of the
FIFO.
Capturing data to the FIFO always begins with a FIFO mode indicator code fol-
lowed by pixel data. The FIFO Mode Indicator is to be stored in the FIFOs at the
beginning of every capture-enabled field, when the data format is changed
mid-field such as transitioning from packed VBI data to planar mode, and when
video capture of a field is asynchronously enabled. The mode status codes are al-
ways stored in planar format. FIFO1 receives two copies of the status code, while
FIFO2 and FIFO3 each receive one copy.
The SOL code is packed in the FIFO with the first valid pixel data byte, which
is the first pixel DWORD for the scan line. The EOL code is packed in the FIFO
with the last valid pixel data byte, which is the last DWORD location written to the
FIFO for the scan line. The EOL code indicates one to four valid bytes. The
VRE/VRO code is stored in the FIFO at the end of a capture-enabled field. The
DMA controller activates the appropriate PCI byte enables by the time a given
DWORD arrives on the output side of the FIFO.
Table 9. Status Bits
Status[3:0]
Description
0110
1110
0010
0001
1101
1001
0101
0100
1100
0000
FM1
FM3
SOL
EOL
EOL
EOL
EOL
VRE
VRO
PXV
FIFO Mode: packed data to follow
FIFO Mode: planar data to follow
First active pixel/data DWORD of scan line
Last active pixel/data DWORD of scan line, 4 Valid Bytes
Last active pixel/data DWORD of scan line, 3 Valid Bytes
Last active pixel/data DWORD of scan line, 2 Valid Bytes
Last active pixel/data DWORD of scan line, 1 Valid Byte
VRESET following an even field–falling edge of FIELD
VRESET following an odd field–rising edge of FIELD
Valid pixel/data DWORD
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