參數(shù)資料
型號: BT849A
英文描述: Single-Chip Video Capture for PCI
中文描述: 單芯片的PCI視頻捕捉
文件頁數(shù): 68/141頁
文件大?。?/td> 1149K
代理商: BT849A
Bt848/848A/849A
Single-Chip Video Capture for PCI
Brooktree
58
F
UNCTIONAL
D
ESCRIPTION
DMA Controller
L848A_A
FIFO Data Stream
Resynchronization
The Bt848 DMA controller is constantly monitoring whether there is a mismatch
between the amount of data expected by the RISC instruction and the amount of
data being provided by the FIFO. The DMA controller then corrects for the mis-
matches and realigns the RISC program and the FIFO data stream.
For example, if the FIFO contains a shorter video line that expected by the RISC
instruction, the DMA controller detects the EOL control code from the FIFO ear-
lier than expected. The DMA controller then aborts the rest of the RISC instruc-
tions until it detects the EOL control code from the RISC program.
If the FIFO contains a longer video line than expected by the RISC instruction,
the DMAC will not detect the EOL control code from the FIFO at the expected
time. The DMAC will continue reading the FIFO data, however it will discard the
additional FIFO data until it reaches the EOL control code from the FIFO.
Similarly, if the FIFO provides a smaller number of scan lines per field than ex-
pected by the RISC program, the end of field control codes from the FIFO
(VRE/VRO) will arrive early. The DMA controller then aborts all RISC instruc-
tions until the SYNC status codes from the RISC instruction match the end of field
status codes from the FIFO.
If the FIFO provides a larger number of scan lines per field than expected by the
RISC program, the end of field control codes from the FIFO (VRE/VRO) will not
arrive at the expected time. Again, the FIFO data is read by the DMAC and dis-
carded until the SYNC status codes from the RISC instruction match the end of
field status codes from the FIFO.
The DMA controller manages all of the above error conditions, but the FIFO
Data Stream Resynchronization interrupt bit will be set as well.
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