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參數(shù)資料
| 型號： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁數(shù)： | 85/194頁 |
| 文件大小： | 797K |
| 代理商： | AM8530H |
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Data Communication Modes Functional Description
AMD
4–33
via bit D4 in WR3. The Enter Hunt Mode bit in WR3 is a command so writing a ‘0’ to it has
no effect.
In Synchronous modes, once character synchronization has been established, Hunt
mode is terminated and must remain so until the end of message has been received. At
this point, the Enter Hunt Mode command can be re-issued for the next message. Issuing
this command prematurely can lead to false character synchronization. Thus, the SYNC/
HUNT status bit in RR0 will be set only when the Enter Hunt Mode command is issued.
The Hunt status of the Receiver is reported in the SYNC/HUNT status bit in RR0 (D4).
This status bit is one of the possible sources of External/Status interrupts, with both tran-
sitions causing an interrupt. This is true even if the SYNC/HUNT bit is set as a result of
the processor issuing the Enter Hunt Mode command.
While in Hunt mode, the receiver path used in establishing character synchronization will
depend on the mode selected. In either case, however, synchronization will be estab-
lished at the beginning of each transmission either through a two character (BISYNC) or a
single character (MONOSYNC) synchronizing pattern. When character synchronization is
established Hunt mode is terminated and the receiver stops scanning the communication
line for the synchronizing pattern. At this point data passes to the Receive Shift Register
and characters are formed by assembling the proper number of consecutive bits following
the synchronizing pattern before being transferred into the Receive Data FIFO.
4.10.1.1
In Synchronous modes, except External SYNC mode, if bit D7 of WR11 is set to ‘0’, the
SYNC pin will be configured as an output and the SCC will drive it Low every time a sync
character is detected in the data stream. Note, however, that the SYNC pin is activated
regardless of character boundaries so any external circuitry using it in Synchronous
modes should respond only to the SYNC pulse that occurs while the receiver is in Hunt
mode. The timing for the SYNC signal is shown in Figure 4–20.
SYNC Detect Output
4.10.1.1.1
The message format for MONOSYNC is shown in Figure 4–21. In this mode, the incom-
ing data are clocked into the Receive Sync Register and compared with the contents of
WR7 on a bit-by-bit basis until a sync character is found. When a sync character is found,
character synchronization is established and data passes to the Receive Shift Register.
MONOSYNC Mode
In this mode, WR6 is always used to open a message being transmitted, and as time fill
when the transmitter has nothing to send.
4.10.1.1.2
The BISYNC message format is shown in Figure 4–22. In this mode, the synchronization
procedure is similar to that of MONOSYNC except that two sync characters are used for
character synchronization instead of one. In this mode, incoming data are shifted into the
Receive Shift Register while the next eight bits are assembled in the Receive Sync Regis-
ter. If these two characters match the programmed characters in WR6 and WR7, respec-
tively, synchronization is established and the incoming data bypasses the Receive Sync
Register and enters the 3-bit delay directly.
BISYNC Mode
In this mode, the concatenation of WR6 with WR7 is always used during transmit and re-
ceive operations.
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| AM85C30-10PC | Enhanced Serial Communications Controller |
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| AM85C30-8PC | Enhanced Serial Communications Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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