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| 型號(hào)： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁(yè)數(shù)： | 36/194頁(yè) |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530H |
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I/O Programming Functional Description
AMD
3–5
D7
W/DMA
REQ
Enable
D6
W/DMA
REQ
Funct.
D5
W/DMA
REQ on
Rx/Tx
D4
D3
D2
Parity
INT
Enable
D1
Tx
INT
Enable
D0
Ext/Sta
INT
Enable
0
0
1
1
0
1
0
1
— Rx INT Disable
— Rx INT on 1st Char. or
Special Condition
— INT on All Rx Char. or
Special Condition
— Rx INT on Special Only
WR1—Interrupt Source IE
3.4.2
The Interrupt Pending (IP) bit for a given source of interrupt may be set by the presence
of an interrupt condition in the SCC and is reset directly by the processor, or indirectly by
some action that the processor may take. If the corresponding IE bit is not set, the IP for
that source of interrupt will never be set. The IP bits in the SCC are read-only via RR3 as
shown above.
Interrupt Pending Bit
D7
0
D6
0
D5
Ch. A
Rx
IP
D4
Ch. A
Tx
IP
D3
Ch. A
Ext/Sta
IP
D2
Ch. B
Rx
IP
D1
Ch. B
Tx
IP
D0
Ch. B
Ext/Sta
IP
RR3—Interrupt Pending
3.4.3
The Interrupt Under Service (IUS) bits are not observable by the processor. An IUS bit is
set during an Interrupt Acknowledge cycle for the highest-priority IP. The IUS bit is used
to control the operation of internal and external daisy chain interrupts. The internal daisy
chain links the six sources of interrupt in a fixed order, chaining the IUS bits for each
source. While an internal IUS bit is set, all lower-priority interrupt requests are masked
off; during an Interrupt Acknowledge cycle the IP bits are also gated into the daisy chain.
This insures that the highest-priority IP selected will have its IUS bit set. At the end of an
interrupt service routine, the processor must issue a Reset Highest IUS Command in
WR0 to re-enable lower-priority interrupts. This is the only way, short of a software or
hardware reset, that an IUS bit may be reset.
Interrupt Under S ervic e Bit
3.4.4
The Disable Lower Chain (DLC) bit in WR9 (D2) is used to disable all SCCs in a lower
position on the external daisy chain. If this bit is set to ‘1’, the IEO pin is driven Low and
prevents lower-priority devices from generating an interrupt request. Note that the IUS bit,
when set, will have the same effect but is not controllable through software, and the point
where lower-priority interrupts are masked off may not correspond to the chip boundary.
Disable Lower Chain Bit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
| AM85C30-16JC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Communications Controller |
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