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參數(shù)資料
| 型號： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁數(shù)： | 181/194頁 |
| 文件大小： | 797K |
| 代理商： | AM8530H |
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SCC Application Notes
AMD
7–32
The Am8530H can also be configured to make the entire system interrupt-driven. The
chip can be set up to interrupt the CPU on external conditions (i.e., a change on a modem
line or a break condition). It can also be set up to cause receive interrupt on first charac-
ter, on all characters, or on one of many special receive conditions (e.g., receiver overrun,
framing error, or end of frame).
The Am7960 can also support a full-duplex operation (point-to-point between two de-
vices). In this case, no collision avoidance scheme needs to be implemented because
only one device can talk on one line at a time. Such a set-up would be very practical for
STAR configurations, or Token Passing Ring, or Loop configurations (shown in Figure
7–20).
In addition to this 1Mb/s LAN using the Am7960, channel B of the Am8530H is configured
to operate a low speed RS-423/RS-232C asynchronous link. The Am26LS29 driver and
the Am26LS32 receiver were added, as shown in Figure 7–18, to provide proper signal
conditioning for the cable.
7.6.4
Two programs have been written for the hardware described and are listed at the end of
this application note. The program for the transmitter is listed under “Software to Transmit
Data At 1Mb/s Using DMA.” The program for the receiver is listed under “Software to Re-
ceive Data At 1Mb/s Using DMA.” These programs enable a file to be read off a disk on
one IBM* PC (XT or AT), transmit it over a shielded coaxial cable to another similar PC**,
and save it onto a disk on the receiving PC. The collision avoidance scheme is imple-
mented in hardware. The software implementation demonstrates that the Am8530H and
Am7960 can be simply configured for a 1Mb/s data communications network. An actual
operating network may need a slightly greater degree of software sophistication.
S oftware Considerations
The file from disk (hard or floppy) is first copied into memory. The length of the file and
starting address is then determined. The Am8530H Serial Communications Controller
must now be initialized for an SDLC mode of operation with DMA request on transmit or
receive.
The initialization scheme for the Am8530H involves setting up the various modes of op-
eration followed by enabling the transmitter, the receiver, and DMA request. The CRC
scheme of the Am8530H is used to ensure data integrity at the receive end. Finally, the
interrupts are enabled if the Interrupt Mode of data transfer is to be used.
It is important to follow the data initialization sequence as shown in the software routine
for correct operation of the SCC. The DMA controller of the PC can then be loaded with
the starting address of the data and the length of file (number of bytes to be transmitted).
The DMA channel must be enabled upon completion of initialization. Data transmission
starts as soon as DMA is enabled. The transmit-underrun latch must be reset by writing a
C0H to WR0 of the Am8530H. This command controls the transmission of CRC at the
end of transmission.
At the receiving station, the address (first byte after flags) of the incoming data is com-
pared with the device address in WR6 of the Am8530H. The remaining data are received
only if an address match occurs. This process does not involve any CPU interaction. The
EOM and CRC errors are indicated in RR0 of the Am8530H.
The length of the message is transmitted first, and then the entire message is transmitted.
Between these two transmissions, flags (7E
H
) are sent on the line.
In this program, CPU polls the Am8530H to determine End-Of-Message (EOM). Using
the same hardware connections, the SCC can be programmed to interrupt on special re-
ceive conditions to indicate an EOM to the CPU.
Channel B of the Am8530H is initialized for asynchronous communication at 19.2 kbaud.
The asynchronous transmit routine polls bit D2 of Read Register 0 to determine a trans-
mit buffer empty condition. Writing a byte of data to the transmit buffer resets this bit.
Address line AD0 differentiates between a command and data access to the Am8530H.
相關PDF資料 |
PDF描述 |
|---|---|
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
| AM85C30-16JC | Enhanced Serial Communications Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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