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參數(shù)資料
| 型號(hào)： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁(yè)數(shù)： | 122/194頁(yè) |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530H |
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Register Description
AMD
6–12
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
0
0
1
1
0
1
1
X1 Clock Mode
X16 Clock Mode
X32 Clock Mode
X64 Clock Mode
Parity Enable
Parity Even/Odd
SYNC Modes Enable
1 Stop Bit/Character
1
1
/
2
Stop Bits/Character
2 Stop Bits/Character
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
8 Bit SYNC Character
16 Bit SYNC Character
SDLC Mode (01111110 Flag)
External SYNC Mode
Figure 6–5. Write Register 4
Bits 7 and 6: Clock Rate 1 And 0
These bits specify the multiplier between the clock and data rates. In synchronous
modes, the 1X mode is forced internally and these bits are ignored unless External Sync
mode has been selected.
1X Mode (00)
. The clock rate and data rate are the same. In External Sync mode, this bit
combination specifies that only the
SYNC
pin can be used to achieve character synchro-
nization.
16X Mode (01)
. The clock rate is 16 times the data rate. In External Sync mode, this bit
combination specifies that only the
SYNC
pin can be used to achieve character synchro-
nization.
32X Mode (10)
. The clock rate is 32 times the data rate. In External Sync mode, this bit
combination specifies that either the
SYNC
pin or a match with the character stored in
WR7 will signal character synchronization. The sync character can be either six or eight
bits long as specified by the 6-bit/8-bit Sync bit in WR10.
64X Mode (11)
. The clock rate is 64 times the data rate. With this bit combination in Ex-
ternal Sync mode, both the receiver and transmitter are placed in SDLC mode. The only
variation from normal SDLC operation is that the
SYNC
pin is used to start or stop the
reception of a frame by forcing the receiver to act as though a flag had been received.
Bits 5 and 4: SYNC Modes 1 And 0
These two bits select the various options for character synchronization. They are ignored
unless synchronous modes are selected in the stop bits field of this register.
Monosync (00)
. In this mode, the receiver achieves character synchronization by match-
ing the character stored in WR7 with an identical character in the received data stream.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
| AM85C30-16JC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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