參數(shù)資料
型號(hào)： ADUC834
廠商： Analog Devices, Inc.
英文描述： MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述： MicroConverter的，雙與嵌入62KB閃存MCU 16-/24-位ADC
文件頁數(shù)： 61/72頁
文件大?。?/td> 1451K
代理商： ADUC834
REV.
P
rC (12 March 2002)
ADuC834
–
61
–
PRELIMINARY TECHNICAL DATA
UART OPE RAT ING MOD E S
Mode 0: 8-Bit Shift Register Mode
Mode 0 is selected by clearing both the SM0 and SM1 bits in
the SFR SCON. Serial data enters and exits through RX D. T X D
outputs the shift clock. Eight data bits are transmitted or re-
ceived. T ransmission is initiated by any instruction that writes to
SBUF. T he data is shifted out of the RX D line. T he eight bits are
transmitted with the least-significant bit (LSB) first, as shown in
Figure 50.
CORE
CLK
ALE
RXD
(DATA OUT)
TXD
(SHIFT CLOCK)
DATA BIT 0
DATA BIT 1
DATA BIT 6
DATA BIT 7
S6
S5
S4
S3
S2
S1
S6
S5
S4
S4
S3
S2
S1
S6
S5
S4
S3
S2
S1
MACHINE
CYCLE 8
MACHINE
CYCLE 7
MACHINE
CYCLE 2
MACHINE
CYCLE 1
Figure 50. UART Serial Port Transmission, Mode 0.
Reception is initiated when the receive enable bit (REN) is 1
and the receive interrupt bit (RI) is 0. When RI is cleared the
data is clocked into the RX D line and the clock pulses are
output from the T X D line.
Mode 1: 8-Bit UART , Variable Baud Rate
Mode 1 is selected by clearing SM0 and setting SM1. Each data
byte (LSB first) is preceded by a start bit(0) and followed by a stop
bit(1). T herefore 10 bits are transmitted on T X D or received on
RX D. T he baud rate is set by the T imer 1 or T imer 2 overflow
rate, or a combination of the two (one for transmission and the
other for reception).
T ransmission is initiated by writing to SBUF. T he
‘
write to
SBUF
’
signal also loads a 1 (stop bit) into the ninth bit position
of the transmit shift register. T he data is output bit by bit
until the stop bit appears on T X D and the transmit interrupt
flag (T I) is automatically set as shown in Figure 51.
TXD
TI
(SCON.1)
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
STOP BIT
SET INTERRUPT
i.e. READY FOR MORE DATA
Figure 51. UART Serial Port Transmission, Mode 0.
Reception is initiated when a 1-to-0 transition is detected on
RX D. Assuming a valid start bit was detected, character reception
continues. T he start bit is skipped and the eight data bits are
clocked into the serial port shift register. When all eight bits have
been clocked in, the following events occur:
- T he eight bits in the receive shift register are latched into SBUF
- T he ninth bit (Stop bit) is clocked into RB8 in SCON
- T he Receiver interrupt flag (RI) is set
if, and only if, the following conditions are met at the time the
final shift pulse is generated:
- RI = 0, and
- Either SM2 = 0, or SM2 = 1 and the received stop bit = 1.
If either of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
Mode 2: 9-Bit UART with F ixed Baud Rate
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode the UART operates in 9-bit mode with a fixed baud rate.
T he baud rate is fixed at Core_Clk/64 by default, although
by setting the SMOD bit in PCON, the frequency can be
doubled to Core_Clk/32. Eleven bits are transmitted or received, a
start bit(0), eight data bits, a programmable ninth bit and a stop
bit(1). T he ninth bit is most often used as a parity bit, although it
can be used for anything, including a ninth data bit if required.
T o transmit, the eight data bits must be written into SBUF.
T he ninth bit must be written to T B8 in SCON. When transmis-
sion is initiated the eight data bits (from SBUF) are loaded
onto the transmit shift register (LSB first). T he contents of T B8
are loaded into the ninth bit position of the transmit shift register.
T he transmission will start at the next valid baud rate clock.
T he T I flag is set as soon as the stop bit appears on T X D.
Reception for Mode 2 is similar to that of Mode 1. T he eight
data bytes are input at RX D (LSB first) and loaded onto the
receive shift register. When all eight bits have been clocked in,
the following events occur:
- T he eight bits in the receive shift register are latched into SBUF
- T he ninth data bit is latched into RB8 in SCON
- T he Receiver interrupt flag (RI) is set
if, and only if, the following conditions are met at the time the
final shift pulse is generated:
- RI = 0, and
- Either SM2 = 0, or SM2 = 1 and the received stop bit = 1.
If either of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
Mode 3: 9-Bit UART with Variable Baud Rate
Mode 3 is selected by setting both SM0 and SM1. In this mode
the 8051 UART serial port operates in 9-bit mode with a variable
baud rate determined by either T imer 1 or T imer 2. T he opera-
tion of the 9-bit UART is the same as for Mode 2 but the baud
rate can be varied as for Mode 1.
In all four modes, transmission is initiated by any instruction that
uses SBUF as a destination register. Reception is initiated in Mode 0
by the condition RI = 0 and REN = 1. Reception is initiated in
the other modes by the incoming start bit if REN = 1.
UART Serial Port Baud Rate Generation
Mode 0 Baud Rate Generation
T he baud rate in Mode 0 is fixed:
Mode 0 Baud Rate = (Core Clock Frequency
1
/12)
NOT E
1
In these descriptions Core Clock Frequency refers to the core clock frequency
selected via the CD0
–
2 bits in the PLLCON SFR.
Mode 2 Baud Rate Generation
T he baud rate in Mode 2 depends on the value of the SMOD bit
in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the core
clock. If SMOD = 1, the baud rate is 1/32 of the core clock:
Mode 2 Baud Rate = (2
SMOD
/64)
∞
(Core Clock Frequency)
Mode 1 and 3 Baud Rate Generation
T raditionally the baud rates in Modes 1 and 3 are determined by
the overflow rate in T imer 1 or T imer 2, or both (one for
transmit and the other for receive).
On the ADuC834 however the baud rate can also be generated
via a seperate baud rate generator to achieve higher baud rates
and allow all three be used for other functions.
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