參數(shù)資料
型號(hào)： ADUC834
廠商： Analog Devices, Inc.
英文描述： MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述： MicroConverter的，雙與嵌入62KB閃存MCU 16-/24-位ADC
文件頁數(shù)： 51/72頁
文件大?。?/td> 1451K
代理商： ADUC834
REV.
P
rC (12 March 2002)
ADuC834
–
51
–
PRELIMINARY TECHNICAL DATA
SE RIAL PE RIPHE RAL INT E RF AC E
T he ADuC834 integrates a complete hardware Serial Periph-
eral Interface (SPI) interface on-chip. SPI is an industry standard
synchronous serial interface that allows eight bits of data to
be synchronously transmitted and received simultaneously, i.e.,
full duplex. It should be noted that the SPI pins SCLOCK and
MOSI are multiplexed with the digital output pins D0 and D1.
T his pins are controlled via the DCON SFR only if SPE is clear.
SPI can be configured for Master or Slave operation and typically
consists of four pins, namely:
SC L OC K (Serial C lock I/O Pin), Pin#26
T he master clock (SC L OC K ) is used to synchronize the
data being transmitted and received through the MOSI and
MISO data lines. A single data bit is transmitted and re-
ceived in each SCLOCK period. T herefore, a byte is
transmitted/received after eight SCLOCK periods. T he
SCLOCK pin is configured as an output in master mode and
as an input in slave mode. In master mode the bit-rate, polarity
and phase of the clock are controlled by the CPOL, CPHA,
SPR0 and SPR1 bits in the SPIC ON SF R (see T able X X I
below). In slave mode the SPIC ON register will have to be
configured with the phase and polarity (CPHA and C POL )
as the master as for both master and slave mode the data is
transmitted on one edge of the SCLOCK signal and sampled
on the other.
MISO (Master In, Slave Out Data I/O Pin), Pin#14
T he MISO (master in slave out) pin is configured as an input
line in master mode and an output line in slave mode. T he
MISO line on the master (data in) should be connected to the
MISO line in the slave device (data out). T he data is trans-
ferred as byte wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin), Pin#27
T he MOSI (master out slave in) pin is configured as an output line
in master mode and an input line in slave mode. T he MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). T he data is transferred as byte
wide (8-bit) serial data, MSB first.
SS
(Slave Select Input Pin), Pin#13
T he Slave Select (
SS
) input pin is only used when the
ADuC834 is configured in SPI slave mode. T his line is active
low. Data is only received or transmitted in slave mode when
the
SS
pin is low, allowing the ADuC834 to be used in single
master, multislave SPI configurations. If CPHA = 1 then the
SS
input may be permanently pulled low. With CPHA = 0 then
the
SS
input must be driven low before the first bit in a byte
wide transmission or reception and return high again after the
last bit in that byte wide transmission or reception. In SPI
Slave Mode, the logic level on the external
SS
pin (Pin# 13),
can be read via the SPR0 bit in the SPICON SFR.
T he following SFR registers are used to control the SPI interface.
T able X X I. SPICON SFR Bit Designations
Description
Bit
Name
7
ISPI
SPI Interrupt Bit.
Set
by MicroConverter at the end of each SPI transfer.
Cleared
directly by user code or indirectly by reading the SPIDAT SFR
Write Collision Error Bit.
Set
by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared
by user code.
SPI Interface Enable Bit.
Set
by user to enable the SPI interface.
Cleared
by user to allow the DCON SFR control the digital output pins D0 and D1
SPI Master/Slave Mode Select Bit.
Set
by user to enable Master Mode operation (SCLOCK is an output).
Cleared
by user to enable Slave Mode operation (SCLOCK is an input).
Clock Polarity Select Bit.
Set
by user if SCLOCK idles high.
Cleared
by user if SCLOCK idles low.
Clock Phase Select Bit.
Set
by user if leading SCLOCK edge is to transmit data.
Cleared
by user if trailing SCLOCK edge is to transmit data.
SPI Bit-Rate Select Bits.
T hese bits select the SCLOCK rate (bit-rate) in Master Mode as follows:
SPR1
SPR0
Selected Bit Rate
0
0
f
CORE
/2
0
1
f
CORE
/4
1
0
f
CORE
/8
1
1
fcore/16
In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external
SS
pin (Pin# 13), can be read
via the SPR0 bit.
6
WCOL
5
SPE
4
SPIM
3
CPOL
2
CPHA
1
0
SPR1
SPR0
NOT E
T he CPOL and CPHA bits should both contain the same values for master and slave devices.
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