參數(shù)資料
型號: ADUC834
廠商: Analog Devices, Inc.
英文描述: MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述: MicroConverter的,雙與嵌入62KB閃存MCU 16-/24-位ADC
文件頁數(shù): 47/72頁
文件大?。?/td> 1451K
代理商: ADUC834
REV.
P
rC (12 March 2002)
ADuC834
47
PRELIMINARY TECHNICAL DATA
T IME INT E RVAL C OUNT E R (T IC )
A time interval counter is provided on-chip for:
- counting longer intervals than the standard
8051-compatible timers are capable of
- periodically the part up from power down
- implementing a Real T ime Clock
T he T IC is capable of timeout intervals ranging from 1/128th
second to 255 hours. Furthermore, this counter is clocked by
the crystal oscillator rather than the PL L and thus has the
ability to remain active in power-down mode and time long
power-down intervals. T his has obvious applications for remote
battery-powered sensors where regular widely spaced readings
are required.
If the T IC is being used as a real time clock (T CEN is set) then
the T CEN bit itself and the HT HSEC, SEC, MIN and HOUR
registers do not get reset after a hardware or watchdog timer
reset. T his is to prevent the need to recalibrate the real time
clock after a reset. However, these registers will get reset to 00h
after a power cycle (independent of T CEN) or after any reset if
T CEN is clear.
Six SFRs are associated with the time interval counter, T IMECON
being its control register. Depending on the configuration of the
IT 0 and IT 1 bits in T IMECON, the selected time counter register
overflow will clock the interval counter. When this counter is
equal to the time interval value loaded in the INT VAL SFR,
the T II bit (T IMECON.2) is set and generates an interrupt if
enabled (See IEIP2 SFR description under Interrupt System
later in this data sheet.) If the ADuC834 is in power-down
mode, again with T IC interrupt enabled, the T II bit will wake
up the device and resume code execution by vectoring directly
to the T IC interrupt service vector address at 0053 hex. T he
T IC-related SFRs are described in T able X VIII. Note also that
the timebase SFRs can be written initially with the current
time, the T IC can then be controlled and accessed by user soft-
ware. In effect, this facilitates the implementation of a real-time
clock. A block diagram of the T IC is shown in Figure 42.
8-BIT
PRESCALER
HUNDREDTHS COUNTER
HTHSEC
SECOND COUNTER
SEC
MINUTE COUNTER
MIN
HOUR COUNTER
HOUR
TIEN
INTERVAL TIMEOUT
TIME INTERVAL COUNTER INTERRUPT
8-BIT
INTERVAL COUNTER
INTVAL SFR
INTERVAL
TIMEBASE
SELECTION
MUX
TCEN
32.768kHz EXTERNAL CRYSTAL
ITS0, 1
EQUAL
Figure 42. TIC, Simplified Block Diagram
T able X VIII. T IME CON SFR Bit Designations
Bit
Name
Description
7
6
5
4
---
---
IT S1
IT S0
Reserved for Future Use.
Reserved for Future Use. For future product code compatibility this bit should be written as a
1.
Interval T imebase Selection Bits.
Written by user to determine the interval counter update rate.
IT S1
IT S0
Interval T imebase
0
0
1/128 Second
0
1
Seconds
1
0
Minutes
1
1
Hours
Single T ime Interval Bit.
Set by user to generate a single interval timeout. If set, a timeout will clear the T IEN bit.
Cleared by user to allow the interval counter to be automatically reloaded and start counting again at
each interval timeout.
T IC Interrupt Bit.
Set when the 8-bit Interval Counter matches the value in the INT VAL SFR.
Cleared
by user software.
T ime Interval Enable Bit.
Set by user to enable the 8-bit time interval counter.
Cleared by user to disable and clear the contents of the interval counter.
T ime Clock Enable Bit.
Set by user to enable the time clock to the time interval counters.
Cleared by user to disable the clock to the time interval counters and clear the time interval SFRs.
T he time registers (HT HSEC, SEC, MIN and HOUR) can be written while T CEN is low.
3
ST I
2
T II
1
T IEN
0
T CEN
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