參數(shù)資料
型號： ADUC834
廠商： Analog Devices, Inc.
英文描述： MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述： MicroConverter的，雙與嵌入62KB閃存MCU 16-/24-位ADC
文件頁數(shù)： 28/72頁
文件大小： 1451K
代理商： ADUC834
(12 March 2002) REV.
P
rC
ADuC834
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28
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PRELIMINARY TECHNICAL DATA
ADC0H/ADC0M/ADC0L (Primary ADC Conversion Result Registers)
T hese three 8-bit registers hold the 24-bit conversion result from the Primary ADC.
SFR Address
ADC0H
ADC0M
ADC0L
Power-On Default Value
00H
Bit Addressable
No
High Data Byte
Middle Data Byte
Low Data Byte
Both registers
Both registers
DBH
DAH
D9H
ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers)
T hese two 8-bit registers hold the 16-bit conversion result from the Auxiliary ADC.
SFR Address
ADC1H
ADC1L
Power-On Default Value
00H
Bit Addressable
No
High Data Byte
Low Data Byte
Both Registers
Both Registers
DDH
DCH
OF0H/OF0M/OF0L (Primary ADC Offset Calibration Registers
1
)
T hese three 8-bit registers hold the 24-bit offset calibration coefficient for the Primary ADC. T hese registers are configured at
power-on with a factory default value of 800000Hex. However, these bytes will be automatically overwritten if an internal or system
zero-scale calibration is initiated by the user via MD2–0 bits in the ADCMODE register.
SFR Address
OF0H
Primary ADC Offset Coefficient High Byte
OF0M
Primary ADC Offset Coefficient Middle Byte
OF0L
Primary ADC Offset Coefficient Low Byte
Power-On Default Value
800000H
OF0H and OF0M Respectively
Bit Addressable
No
Both Registers
E3H
E2H
E1H
OF1H/OF1L (Auxiliary ADC Offset Calibration Registers
1
)
T hese two 8-bit registers hold the 16-bit offset calibration coefficient for the Auxiliary ADC. T hese registers are configured at power-
on with a factory default value of 8000Hex. However, these bytes will be automatically overwritten if an internal or system zero-scale
calibration is initiated by the user via the MD2–0 bits in the ADCMODE register.
SFR Address
OF1H
Auxiliary ADC Offset Coefficient High Byte
OF1L
Auxiliary ADC Offset Coefficient Low Byte
Power-On Default Value
8000H
OF1H and OF1L Respectively
Bit Addressable
No
Both Registers
E5H
E4H
GN0H/GN0M/GN0L (Primary ADC Gain Calibration Registers
1
)
T hese three 8-bit registers hold the 24-bit gain calibration coefficient for the Primary ADC. T hese registers are configured at
power-on with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. How-
ever, these bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2–0
bits in the ADCMODE register.
SFR Address
GN0H
Primary ADC Gain Coefficient High Byte
GN0M
Primary ADC Gain Coefficient Middle Byte
GN0L
Primary ADC Gain Coefficient Low Byte
Power-On Default Value
Configured at factory final test, see notes above.
Bit Addressable
No
Both Registers
EBH
EAH
E9H
GN1H/GN1L (Auxiliary ADC Gain Calibration Registers
1
)
T hese two 8-bit registers hold the 16-bit gain calibration coefficient for the Auxiliary ADC. T hese registers are configured at power-
on with a factory calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However,
these bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2–0 bits in
the ADCMODE register.
SFR Address
GN1H
Auxiliary ADC Gain Coefficient High Byte
GN1L
Auxiliary ADC Gain Coefficient Low Byte
Power-On Default Value
Configured at factory final test, see notes above.
Bit Addressable
No
Both Registers
EDH
ECH
NOT E
1
T hese registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero.
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