參數(shù)資料
型號(hào)： ADUC834
廠商： Analog Devices, Inc.
英文描述： MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述： MicroConverter的，雙與嵌入62KB閃存MCU 16-/24-位ADC
文件頁(yè)數(shù)： 25/72頁(yè)
文件大?。?/td> 1451K
代理商： ADUC834
REV.
P
rC (12 March 2002)
ADuC834
–
25
–
PRELIMINARY TECHNICAL DATA
USE R INT E RFACE T O T HE PRIMARY AND
AUX ILIARY ADCS
Both ADCs are controlled and configured via a number of
SFRs that are mentioned here and described in more detail
in the following pages.
ADCST AT :
ADC Status Register. Holds general status of
the Primary and Auxiliary ADCs.
ADCMODE:
ADC Mode Register. Controls general modes
of operation for Primary and Auxiliary ADCs.
ADC0CON:
Primary ADC C ontrol Register. Controls
specific configuration of Primary ADC.
ADC1CON:
Auxiliary ADC Control Register. Controls
specific configuration of Auxiliary ADC.
SF:
Sinc Filter Register. Configures the decimation
factor for the Sinc
3
filter and thus the Primary
and Auxiliary ADC update rates.
ICON:
Current Source Control Register. Allows
user control of the various on-chip current
source options.
ADC0L/M/H:
Primary ADC 24-bit conversion result held
in these three 8-bit registers.
Auxiliary ADC 16-bit conversion result held
in these two 8-bit registers.
Primary ADC 24-bit Offset Calibration Coeffi-
cient held in these three 8-bit registers.
Auxiliary ADC 16-bit Offset Calibration
Coefficient held in these two 8-bit registers.
Primary ADC 24-bit Gain Calibration
Coefficient held in these three 8-bit registers.
Auxiliary ADC 16-bit Gain Calibration Coeffi-
cient held in these two 8-bit registers.
ADC1L/H:
OF0L/M/H:
OF1L/H:
GN0L/M/H:
GN1L/H:
ADCST AT —(ADC Status Register)
T his SFR reflects the status of both ADCs including data ready, calibration and various (ADC-related) error and warning condi-
tions including reference detect and conversion overflow/underflow flags.
SFR Address
D8H
Power-On Default Value
00H
Bit Addressable
Yes
T able IV. ADCST AT SFR Bit Designations
Bit
Name
Description
7
RDY0
Ready Bit for Primary ADC.
Set
by hardware on completion of ADC conversion or calibration cycle.
Cleared
directly by the user or indirectly by write to the mode bits to start another Primary
ADC conversion or calibration. T he Primary ADC is inhibited from writing further results to its
data or calibration registers until the RDY0 bit is cleared.
Ready Bit for Auxiliary ADC.
Same definition as RDY 0 referred to the Auxiliary ADC.
Calibration Status Bit.
Set
by hardware on completion of calibration.
Cleared
indirectly by a write to the mode bits to start another ADC conversion or calibration.
No External Reference Bit (only active if Primary or Auxiliary ADC is active).
Set
to indicate that one or both of the REFIN pins is floating or the applied voltage is below
a specified threshold. When Set conversion results are clamped to all ones, if using ext.
reference.
Cleared
to indicate valid V
REF
.
Primary ADC Error Bit.
Set
by hardware to indicate that the result written to the Primary ADC data registers has
been clamped to all zeros or all ones. After a calibration this bit also flags error conditions that
caused the calibration registers not to be written.
Cleared
by a write to the mode bits to initiate a conversion or calibration.
Auxiliary ADC Error Bit.
Same definition as ERR0 referred to the Auxiliary ADC.
Reserved for Future use.
Reserved for Future use.
6
RDY1
5
CAL
4
NOX REF
3
ERR0
2
ERR1
1
0
---
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