參數(shù)資料
型號： ADUC834
廠商： Analog Devices, Inc.
英文描述： MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述： MicroConverter的，雙與嵌入62KB閃存MCU 16-/24-位ADC
文件頁數(shù)： 41/72頁
文件大小： 1451K
代理商： ADUC834
REV.
P
rC (12 March 2002)
ADuC834
–
41
–
PRELIMINARY TECHNICAL DATA
Using the D/A Converter
T he on-chip D/A converter architecture consists of a resistor
string DAC followed by an output buffer amplifier, the func-
tional equivalent of which is illustrated in Figure 30.
OUTPUT
BUFFER
HIGH Z
DISABLE
(FROM MCU)
DAC0
R
R
R
R
R
ADuC834
AVDD
VREF
20
Figure 30. Resistor String DAC Functional Equivalent
Features of this architecture include inherent guaranteed mono-
tonicity and excellent differential linearity. As illustrated in
Figure 30, the reference source for each DAC is user selectable
in software. It can be either AV
DD
or V
REF.
In 0-to-AV
DD
mode,
the DAC output transfer function spans from 0V to the volt-
age at the AV
DD
pin. In 0-to-V
REF
mode, the DAC output
transfer function spans from 0V to the internal V
REF
(2.5V).
T he DAC output buffer amplifier features a true rail-to-rail
output stage implementation. T his means that, unloaded, each
output is capable of swinging to within less than 100mV of both
AV
DD
and ground. Moreover, the DAC
’
s linearity specification
(when driving a 10K
resistive load to ground) is guaranteed
through the full transfer function
except
codes 0 to 48, and, in 0-
to-AV
DD
mode only, codes 3945 to 4095.
Linearity degradation near ground and V
DD
is caused by satura-
tion of the output amplifier, and a general representation of its
effects (neglecting offset & gain error) is illustrated in Figure
31. T he dotted line in Figure 31 indicates the
ideal
transfer
function, and the solid line represents what the transfer func-
tion might look like with endpoint non-linearities due to
saturation of the output amplifier.
DAC
T he ADuC834 incorporates a 12-bit, voltage output DAC on-
chip. It has a rail-to-rail voltage output buffer capable of driving
10 k
/100 pF. It has two selectable ranges, 0 V to V
REF
(the
internal bandgap 2.5 V reference) and 0 V to AV
DD
. It can
operate in 12-bit or 8-bit mode. T he DAC has a control regis-
ter, DACCON, and two data registers, DACH/L. T he DAC
output can be programmed to appear at Pin 3 or Pin 12. It
should be noted that in 12-bit mode, the DAC voltage output
will be updated as soon as the DACL data SFR has been writ-
ten; therefore, the DAC data registers should be updated as
DACH first followed by DACL.
5
T he 12-bit DAC data should
be written into DACH/L right-justified such that DACL con-
tains the lower eight bits, and the lower nibble of DACH
contains the upper four bits.
T able X V. DACCON SFR Bit Designations
Bit
Name
Description
7
6
5
4
---
---
---
DACPIN
Reserved for Future Use.
Reserved for Future Use.
Reserved for Future Use.
DAC Output Pin Select.
Set
by the user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC).
Cleared
by user to direct the DAC output to Pin 3 (P1.2/DAC/IEX C1).
DAC 8-bit Mode Bit.
Set
by user to enable 8-bit DAC operation. In this mode the 8-bits in DACL SFR are routed to
the 8 MSBs of the DAC and the 4 LSBs of the DAC are set to zero.
Cleared
by user to operate the DAC in its normal 12-bit mode of operation.
DAC Output Range Bit.
Set
by user to configure DAC range of 0
–
AV
DD
.
Cleared
by user to configure DAC range of 0
–
2.5V (V
REF
).
DAC Clear Bit.
Set
to
‘
1
’
by user to enable normal DAC operation.
Cleared
to
‘
0
’
by user to reset DAC data registers DACl/H to zero.
DAC Enable Bit.
Set
to
‘
1
’
by user to enable normal DAC operation.
Cleared
to
‘
0
’
by user to power-down the DAC.
3
DAC8
2
DACRN
1
DACCLR
0
DACEN
DAC H/L
Function
SFR Address
DAC Data Registers
DAC Data Registers, written by user to update the DAC output.
DACL (DAC Data Low Byte)
DACH (DAC Data High Byte)
00H
No
–
>FBH
–
>FCH
–
>Both Registers
–
>Both Registers
Power-On Default Value
Bit Addressable
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