參數(shù)資料
型號： ADUC834
廠商： Analog Devices, Inc.
英文描述： MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述： MicroConverter的，雙與嵌入62KB閃存MCU 16-/24-位ADC
文件頁數(shù)： 33/72頁
文件大?。?/td> 1451K
代理商： ADUC834
REV.
P
rC (12 March 2002)
ADuC834
–
33
–
PRELIMINARY TECHNICAL DATA
Analog Input C hannels
T he primary ADC has four associated analog input pins (la-
belled AIN1 to AIN4) which can be configured as two fully
differential input channels. Channel selection bits in the
ADC0CON SFR detailed in T able VI allow three combina-
tions of differential pair selection as well as an additional shorted
input option (AIN2–AIN2).
T he auxiliary ADC has three external input pins (labelled
AIN3 to AIN5) as well as an internal connection to the internal
on-chip temperature sensor. All inputs to the auxiliary ADC
are single-ended inputs referenced to the AGND on the part.
C hannel selection bits in the ADC 1C ON SFR detailed pre-
viously in T able VII allow selection of one of four inputs.
T wo input multiplexers switch the selected input channel to
the on-chip buffer amplifier in the case of the primary ADC
and directly to the sigma-delta modulator input in the case
of the auxiliary ADC. When the analog input channel is
switched, the settling time of the part must elapse before a new
valid word is available from the ADC.
Primary and Auxiliary ADC Inputs
T he output of the primary ADC multiplexer feeds into a
high impedance input stage of the buffer amplifier. As a
result, the primary ADC inputs can handle significant source
impedances and are tailored for direct connection to external
resistive-type sensors like strain gauges or Resistance T empera-
ture Detectors (RT Ds).
T he auxiliary ADC, however, is unbuffered resulting in higher
analog input current on the auxiliary ADC. It should be noted
that this unbuffered input path provides a dynamic load to the
driving source. T herefore, resistor/capacitor combinations on
the input pins can cause dc gain errors depending on the output
impedance of the source that is driving the ADC inputs.
Analog Input Ranges
T he absolute input voltage range on the primary ADC is re-
stricted to between AGND + 100 mV to AVDD –100 mV. Care
must be taken in setting up the common-mode voltage and
input voltage range so that these limits are not exceeded, other-
wise there will be a degradation in linearity performance.
T he absolute input voltage range on the auxiliary ADC is re-
stricted to between AGND – 30 mV to AVDD + 30 mV. T he
slightly negative absolute input voltage limit does allow the
possibility of monitoring small signal bipolar signals using the
single-ended auxiliary ADC front end.
Programmable Gain Amplifier
T he output from the buffer on the primary ADC is applied to
the input of the on-chip programmable gain amplifier (PGA).
T he PGA can be programmed through eight different unipolar
input ranges and bipolar ranges. T he PGA gain range is pro-
grammed via the range bits in the ADC0CON SFR. With the
external reference select bit set in the ADC0CON SFR and an
external 2.5V reference, the unipolar ranges are 0 mV to
+20 mV, 0 mV to 40 mV, 0 mV to 80 mV, 0 mV to 160 mV,
0 mV to 320 mV, 0 mV to 640 mV and 0 V to 1.28 V and 0
to 2.56 V while the bipolar ranges are ±20 mV, ±40 mV,
±80 mV, ±160 mV, ±320 mV, ±640 mV, ±1.28 V and
±2.56 V. T hese are the nominal ranges that should appear at the
input to the on-chip PGA. An ADC range matching specifica-
tion of 0.5 LSB (typ) across all ranges means that calibration
need only be carried out at a single gain range and does not
have to be repeated when the PGA gain range is changed.
T ypical matching across ranges is shown in Figure 19 below.
Here, the primary ADC is configured in bipolar mode with an
external 2.5 V reference, while just greater than 19 mV is
forced on its inputs. T he ADC continuously converts the DC
input voltage at an update rate of 5.35 Hz, i.e., SF = FFhex. In
total, 800 conversion results are gathered. T he first 100 re-
sults are gathered with the primary ADC operating in the
±20 mV range. T he ADC range is then switched to ±40 mV and
100 more conversion results are gathered, and so on until the
last group of 100 samples are gathered with the ADC configured
in the ±2.56 V range. F rom F igure 19, T he variation in the
sample mean through each range, i.e., the range matching, is
seen to be of the order of 2 μV.
T he auxiliary ADC does not incorporate a PGA and is config-
ured for a fixed single input range of 0 to V
REF
.
0
100
200
300
400
1
500
600
700
800
SAMPLE COUNT
A
19.372
19.371
19.370
19.369
19.368
19.367
19.366
19.365
19.364
ADC RANGE
2
4
8
3
6
1
2
Figure 19. Primary ADC Range Matching
Bipolar/Unipolar Inputs
T he analog inputs on the ADuC 834 can accept either uni-
polar or bipolar input voltage ranges. Bipolar input ranges
do not imply that the part can handle negative voltages with
respect to system AGND.
Unipolar and bipolar signals on the AIN(+) input on the pri-
mary ADC are referenced to the voltage on the respective AIN(–)
input. For example, if AIN(–) is 2.5 V and the primary ADC is
configured for an analog input range of 0 mV to +20 mV,
the input voltage range on the AIN(+) input is 2.5 V to
2.52 V. If AIN(–) is 2.5 V and the ADuC834 is configured for an
analog input range of 1.28 V, the analog input range on the
AIN(+) input is 1.22 V to 3.78 V (i.e., 2.5 V ± 1.28 V).
As mentioned earlier, the auxiliary ADC input is a single-
ended input with respect to the system AGND. In this context a
bipolar signal on the auxiliary ADC can only span 30 mV
negative with respect to AGND before violating the voltage
input limits for this ADC.
Bipolar or unipolar options are chosen by programming the
Primary and Auxiliary Unipolar enable bits in the ADC0CON
and ADC1CON SFRs respectively. T his programs the relevant
ADC for either unipolar or bipolar operation. Programming for
either unipolar or bipolar operation does not change any of the
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