參數(shù)資料
型號: ADUC834
廠商: Analog Devices, Inc.
英文描述: MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述: MicroConverter的,雙與嵌入62KB閃存MCU 16-/24-位ADC
文件頁數(shù): 22/72頁
文件大小: 1451K
代理商: ADUC834
(12 March 2002) REV.
P
rC
ADuC834
22
PRELIMINARY TECHNICAL DATA
E xternal Data Memory (E xternal X RAM)
Just like a standard 8051 compatible core the ADuC834 can
access external data memory using a MOVX instruction. T he
MOVX instruction automatically outputs the various control
strobes required to access the data memory.
T he ADuC834 however, can access up to 16MBytes of extrenal
data memory. T his is an enhancement of the 64kBytes external
data memory space available on a standard 8051 compatible
core.
T he external data memory is discussed in more detail in the
ADuC834 Hardware Design Considerations section.
Internal X RAM
2kBytes of on-chip data memory exist on the ADuC834. T his
memory although on-chip is also accessed via the MOVX in-
struction. T he 2kBytes of internal X RAM are mapped into the
bottom 2kBytes of the external address space if the CFG834.0
bit is set, otherwise access to the external data memory will
occur just like a standard 8051.
Even with the CFG834.0 bit set access to the external X RAM
will occur once the 24 bit DPT R is greater than 0007FFH.
When accessing the internal X RAM the P0, P2 port pins as well
as the RD and WR strobes will not be output as per a standard
8051 MOVX instruction. T his allows the user to use these port
pins as standard I/O.
EXTERNAL
DATA
MEMORY
SPACE
(24-BIT
ADDRESS
SPACE)
000000H
FFFFFFH
CFG834.0=0
EXTERNAL
DATA
MEMORY
SPACE
(24-BIT
ADDRESS
SPACE)
000000H
FFFFFFH
CFG834.0=1
0007FFH
000800H
2 KBYTES
ON-CHIP
XRAM
Figure 14. Internal and External X RAM
SPE CIAL FUNCT ION RE GIST E RS (SFRs)
T he SFR space is mapped into the upper 128 bytes of internal
data memory space and accessed by direct addressing only. It
provides an interface between the CPU and all on chip periph-
erals. A block diagram showing the programming model of the
ADuC834 via the SFR area is shown in Figure 15.
All registers except the Program Counter (PC) and the four
general-purpose register banks, reside in the SFR area. T he
SFR registers include control, configuration, and data regis-
ters that provide an interface between the CPU and all on-chip
peripherals.
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
62 KBYTE ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE FLASH/EE
PROGRAM MEMORY
8051-
COMPATIBLE
CORE
OTHER ON-CHIP
PERIPHERALS
TEMP SENSOR
CURRENT SOURCES
12-BIT DAC
SERIAL I/O
WDT, PSM
TIC, PLL
DUAL
SIGMA-DELTA
ADCs
4 KBYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE DATA
MEMORY
256 BYTES RAM
2K XRAM
Figure 15. Programming Model
Accumulator SF R (AC C )
ACC is the Accumulator register and is used for math opera-
tions including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. T he mnemonics for
accumulator-specific instructions refer to the Accumulator as
A.
B SFR (B)
T he B register is used with the ACC for multiplication and
division operations. For other instructions it can be treated
as a general-purpose scratchpad register.
Stack Pointer (SP and SPH)
T he SP SFR is the stack pointer and is used to hold an internal
RAM address that is called the ‘top of the stack.’ T he SP register
is incremented before data is stored during PUSH and CALL
executions. While the Stack may reside anywhere in on-chip
RAM, the SP register is initialized to 07H after a reset. T his
causes the stack to begin at location 08H.
As mentioned earlier the ADuC834 offers an extended 11-bit
stack pointer. T he 3 extra bits to make up the 11-bit stack
pointer are the 3 LSBs of the SPH byte located at B7h.
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