參數(shù)資料
型號: ADUC834
廠商: Analog Devices, Inc.
英文描述: MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述: MicroConverter的,雙與嵌入62KB閃存MCU 16-/24-位ADC
文件頁數(shù): 20/72頁
文件大?。?/td> 1451K
代理商: ADUC834
(12 March 2002) REV.
P
rC
ADuC834
20
PRELIMINARY TECHNICAL DATA
Pin No.
Mnemonic
T ype
*
Description
28–31
36-39
P2.0–P2.7
(A8–A15)
(A16–A23)
I/O
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s
written to them are pulled high by the internal pull-up resistors, and in that state can
be used as inputs. As inputs, Port 2 pins being pulled externally low will source current
because of the internal pull-up resistors.
Port 2 emits the high order address bytes during fetches from external program
memory and middle and high order address bytes during accesses to the 24-bit
external data memory space.
32
33
X T AL1
X T AL2
I
O
Input to the crystal oscillator inverter.
Output from the crystal oscillator inverter. (see page 68 for description)
40
EA
I/O
External Access Enable, Logic Input. When held high, this input enables the device
to fetch code from internal program memory locations 0000h to F800h. When held
low this input enables the device to fetch all instructions from external program
memory. T o determine the mode of code execution, i.e., internal or external, the
EA
pin is sampled at the end of an external RESET assertion or as part of a device
power cycle.
EA
may also be used as an external emulation I/O pin and therefore the voltage
level at this pin must not be changed during normal mode operation as it may
cause an emulation interrupt that will halt code execution.
41
PSEN
O
Program Store Enable, Logic Output. T his output is a control signal that enables
the external program memory to the bus during external fetch operations. It is
active every six oscillator periods except during external data memory accesses.
T his pin remains high during internal program execution.
PSEN
can also be used to enable serial download mode when pulled low through a
resistor at the end of an external RESET assertion or as part of a device power cycle.
42
ALE
O
Address Latch Enable, Logic Output. T his output is used to latch the low byte (and
page byte for 24-bit data address space accesses) of the address to external memory
during external code or data memory access cycles. It is activated every six oscillator
periods except during an external data memory access. It can be disabled by setting
the PCON.4 bit in the PCON SFR.
43–46
49–52
P0.0–P0.7
(AD0–AD3)
(AD4–AD7)
I/O
P0.0–P0.7, these pins are part of Port0 which is an 8-bit open-drain bidirectional
I/O port. Port 0 pins that have 1s written to them float and in that state can be used
as high impedance inputs. An external pull-up resistor will be required on P0
outputs to force a valid logic high level externally. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program or data memory.
In this application it uses strong internal pull-ups when emitting 1s.
*I = Input, O = Output, S = Supply.
NOT ES
1. In the following descriptions, SET implies a Logic 1 state and CLEARED implies a Logic 0 state unless otherwise stated.
2. In the following descriptions, SET and CLEARED also imply that the bit is set or automatically cleared by the ADuC834 hardware unless otherwise stated.
3. User software should not write 1s to reserved or unimplemented bits as they may be used in future products.
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