參數(shù)資料
型號: ADUC834
廠商: Analog Devices, Inc.
英文描述: MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述: MicroConverter的,雙與嵌入62KB閃存MCU 16-/24-位ADC
文件頁數(shù): 60/72頁
文件大?。?/td> 1451K
代理商: ADUC834
(12 March 2002) REV.
P
rC
ADuC834
60
PRELIMINARY TECHNICAL DATA
UART SE RIAL INT E RF AC E
T he serial port is full duplex, meaning it can transmit and re-
ceive simultaneously. It is also receive-buffered, meaning it can
commence reception of a second byte before a previously re-
ceived byte has been read from the receive register. However, if
the first byte still has not been read by the time reception of the
second byte is complete, the first byte will be lost. T he physical
interface to the serial data network is via Pins RX D(P3.0) and
T X D(P3.1) while the SFR interface to the UART is com-
prised of the following registers.
SBUF
T he serial port receive and transmit registers are both accessed
through the SBUF SFR (SFR address = 99 hex). Writing to
SBUF loads the transmit register and reading SBUF accesses a
physically separate receive register.
SC ON
SFR Address
Power-On Default Value
Bit Addressable
UART Serial Port C ontrol Register
98H
00H
Yes
T able X X X . SCON SFR Bit Designations
Description
Bit
Name
7
6
SM0
SM1
UART Serial Mode Select Bits.
T hese bits select the Serial Port operating mode as follows:
SM0
SM1
Selected Operating Mode
0
0
Mode 0: Shift Register, fixed baud rate (Core_Clk/2)
0
1
Mode 1: 8-bit UART , variable baud rate
1
0
Mode 2: 9-bit UART , fixed baud rate (Core_Clk/64) or (Core_Clk/32)
1
1
Mode 3: 9-bit UART , variable baud rate
Multiprocessor Communication Enable Bit.
Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is
cleared, RI will be set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is
set, RI will not be activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI will
be set as soon as the byte of data has been received.
Serial Port Receive Enable Bit.
Set
by user software to enable serial port reception.
Cleared
by user software to disable serial port reception.
Serial Port T ransmit (Bit 9).
T he data loaded into T B8 will be the ninth data bit that will be transmitted in Modes 2 and 3.
Serial port Receiver Bit 9.
T he ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1 the stop bit is
latched into RB8.
Serial Port T ransmit Interrupt Flag.
Set
by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in
Modes 1, 2, and 3.
T I must be cleared by user software.
Serial Port Receive Interrupt Flag.
Set
by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in
Modes 1, 2, and 3.
RI must be cleared by software.
5
SM2
4
REN
3
T B8
2
RB8
1
T I
0
RI
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