參數(shù)資料
型號： ADUC834
廠商： Analog Devices, Inc.
英文描述： MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述： MicroConverter的，雙與嵌入62KB閃存MCU 16-/24-位ADC
文件頁數(shù)： 43/72頁
文件大小： 1451K
代理商： ADUC834
REV.
P
rC (12 March 2002)
ADuC834
–
43
–
PRELIMINARY TECHNICAL DATA
PULSE WIDT H MODULAT OR BLOCK (PWM)
T he PWM is one of the new features of the ADuC834 over the
ADuC824. T he PWM can be configured as a
Σ
DAC with up
to 16-bits of resolution or as a PWM with variable resolution.
T he PWM is widely programmable in terms input clock, clock
dividers and PWM mode to produce a highly flexible PWM. A
block diagram of the PWM is shown in figure X , with each of
the modes explained overleaf.
T he PWM uses 5 extra SFRs; the control SFR, PWMCON,
and 4 data SFRs PWM0H, PWM0L, PWM1H and PWM1L.
PWMCON (as described below) controls the different modes
as well as the clock frequency.
PWM0H/L and PWM1H/L are the data regaisters that deter-
mine the outputs at P1.0 and P1.1.
P
WMCON
SFR Address
Power-On Default Value
Bit Addressable
PWM Control SFR
AEh
00h
No
T able X VI. PWMCON SFR Bit Designations
Bit
Name
Description
7
6
5
4
-
MD2
MD1
MD0
Reserved for future use
PWM Mode Bits
T he MD2/1/0 bits choose the PWM mode as follows
MD2
MD1
MD0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PWM Clock Divider
Scale the clock source for the PWM counter as shown below.
CDIV1 CDIV0 Description
0
0
PWM Counter = Selected Clock /1
0
1
PWM Counter = Selected Clock /4
1
0
PWM Counter = Selected Clock /16
1
1
PWM Counter = Selected Clock /64
PWM Clock Divider
Select the clock source for the PWM as shown below.
CSEL1 CSEL0 Description
0
0
PWM Clock = f
X T AL
/15
0
1
PWM Clock = f
X T AL
1
0
PWM Clock = External Interrupt on P3.4/T 0
1
1
PWM Clock = f
VCO
(12.58MHz)
Mode
Mode 0: PWM Disabled
Mode 1: Single variable resolution PWM
Mode 2: T win 8-bit PWM
Mode 3: T win 16-bit PWM
Mode 4: Dual NRZ 16-bit
Σ
DAC
Mode 5: Dual 8-bit PWM
Mode 6: Dual RZ 16-bit
Σ
DAC
Reserved for future use
3
2
CDIV1
CDIV0
1
0
CSEL1
CSEL0
CLOCK
SELECT
PROG
DIVIDER
COMPARE
MODE
PWM0H/L
PWM1H/L
MD2
MD1
MD0
12.583MHz
T0
32.768kHz
32.768kHz/15
P1.0
P1.1
16 BIT PWM COUNTER
CLKSEL0
CLKSEL1
CLKDIV0
CLKDIV1
Figure 35. PWM Block Diagram
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