
(12 March 2002) REV.
P
rC
ADuC834
–
54
–
PRELIMINARY TECHNICAL DATA
8051-COMPAT IBLE ON-CHIP PE RIPHE RALS
T his section gives a brief overview of the various secondary pe-
ripheral circuits are also available to the user on-chip. T hese
remaining functions are fully 8051-compatible and are controlled
via standard 8051 SFR bit definitions.
Parallel I/O Ports 0
–
3
T he ADuC834 uses four input/output ports to exchange data
with external devices. In addition to performing general-pur-
pose I/O, some ports are capable of external memory operations;
others are multiplexed with an alternate function for the periph-
eral features on the device. In general, when a peripheral is
enabled, that pin may not be used as a general purpose I/O pin.
Port 0 is an 8-bit open drain bidirectional I/O port that is di-
rectly controlled via the Port 0 SFR (SFR address = 80 hex).
Port 0 pins that have 1s written to them via the Port 0 SFR will
be configured as open drain and will therefore float. In that
state, Port 0 pins can be used as high impedance inputs. An
external pull-up resistor will be required on Port 0 outputs to
force a valid logic high level externally. Port 0 is also the multi-
plexed low-order address and data bus during accesses to external
program or data memory. In this application it uses strong internal
pull-ups when emitting 1s.
Port 1 is also an 8-bit port directly controlled via the P1 SFR
(SFR address = 90 hex). T he Port 1 pins are divided into two
distinct pin groupings.
P1.0 and P1.1 pins on Port 1 are bidirectional digital I/O pins with
internal pull-ups. If P1.0 and P1.1 have 1s written to them via the
P1 SFR, these pins are pulled high by the internal pull-up resis-
tors. In this state they can also be used as inputs; as input pins
being externally pulled low, they will source current because of
the internal pull-ups. With 0s written to them, both these pins
will drive a logic low output voltage (VOL) and will be capable of
sinking 10 mA compared to the standard 1.6 mA sink capa-
bility on the other port pins. T hese pins also have various
secondary functions described in T able X X III.
T able X X III. Port 1, Alternate Pin Functions
Pin
Alternate Function
P1.0
T 2 (T imer/Counter 2 External Input)
PWM0 (PWM0 output at this pin)
T 2EX (T imer/Counter 2 Capture/Reload T rigger)
PWM1 (PWM1 output at this pin)
P1.1
T he remaining Port 1 pins (P1.2
–
P1.7) can only be configured
as Analog Input (ADC), Analog Output (DAC) or Digital Input
pins. By (power-on) default these pins are configured as Analog
Inputs, i.e.,
‘
1
’
written in the corresponding Port 1 register bit.
T o configure any of these pins as digital inputs, the user should
write a
‘
0
’
to these port bits to configure the corresponding pin
as a high impedance digital input.
Port 2 is a bidirectional port with internal pull-up resistors directly
controlled via the P2 SFR (SFR address = A0 hex). Port 2 pins
that have 1s written to them are pulled high by the internal pull-
up resistors and, in that state, they can be used as inputs. As
inputs, Port 2 pins being pulled externally low will source current
because of the internal pull-up resistors. Port 2 emits the
high order address bytes during fetches from external pro-
gram memory and middle and high order address bytes during
accesses to the 16-bit external data memory space.
Port 3 is a bidirectional port with internal pull-ups directly
controlled via the P2 SFR (SFR address = B0 hex). Port 3
pins that have 1s written to them are pulled high by the internal
pull-ups and in that state they can be used as inputs. As inputs,
Port 3 pins being pulled externally low will source current because
of the internal pull-ups. Port 3 pins also have various secondary
functions described in T able X X IV.
T able X X IV. Port 3, Alternate Pin Functions
Pin
Alternate Function
P3.0
RX D (UART Input Pin)
(or Serial Data I/O in Mode 0)
T X D (UART Output Pin)
(or Serial Clock Output in Mode 0)
INT 0
(External Interrupt 0)
INT 1
(External Interrupt 1)
T 0 (T imer/Counter 0 External Input)
T 1 (T imer/Counter 1 External Input)
WR
(External Data Memory Write Strobe)
RD
(External Data Memory Read Strobe)
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
T he alternate functions of P1.0, P1.1, and Port 3 pins can only be
activated if the corresponding bit latch in the P1 and P3 SFRs
contains a 1. Otherwise, the port pin is stuck at 0. In the case
of the PWM outputs at P1.0 and P1.1, the PWM outputs will
overwrite anything written to P1.0 or P1.1.
Additional Digital Ouput Pins
Pins P1.0 and P1.1 can be used to provide high current (10mA
sink) general purpose I/O. In addition to P1.0 and P1.1, two more
high current (8mA sink)
outputs
are provided at D0 and D1. If
the SPE bit (in SPICON) is clear, the two extra high current
digital ouputs, D0 and D1, are controlled via the DCON SFR as
follows:
T able X X V. DCON SFR description
Bit
Name
Description
7
D1
Data written to this bit will be
outputted on the D1 pin if
D1EN is set.
Set to enable the D1 bit as
an ouput.
Data written to this bit will be
outputted on the DC0 pin if
D0EN is set.
----
Set to enable the D0 bit as
an ouput.
----
----
----
6
D1EN
5
D0
4
3
----
D0EN
2
1
0
----
----
----